System Bus - HP Vectra VL800 Technical Reference Manual

System Bus

The system bus of the Pentium 4 processor is implemented in the AGTL+
(Assisted Gunning Transceiver Logic)+ technology. This technology
features open-drain signal drivers that are pulled up through resistors at bus
extremities to the operating voltage of the processor core. These resistors
also act as bus terminators, and are integrated in the processor and in the
82850 MCH.
Socket 423
Address (32)
Control
Data (64)
AGP 4x Bus
(133 MHz (1 GB/sec
1.5V
data transfer rate)
AGP
Connector
The supported operating frequency of the AGTL+ bus for the Pentium 4 is
100 MHz. The width of the data bus is 64 bits, while the width of the address
is 32 bits. Data bus transfers occur at four times the system bus, at 400 MHz.
Along with the operating frequencies, the processor voltage is set
automatically.
The control signals of the system bus allow the implementation of a "split -
transaction" bus protocol. This allows the Pentium 4 processor to send its
request (for example, for the contents of a given memory address) and then
to release the bus, rather than waiting for the result, thereby allowing it to
Intel Pentium 4
Processor
850
Dual Rambus Channel
Memory
Controller Hub
3.2 GB/s at 400
(MCH)
MHzdata transfer
82850
HUB LINK 8
(266 MB/s data
transfer rate)
I/O Controller Hub
(ICH) 82801AA
100 MHz two-way System Bus
(Data Bus runs at 4 x 100 MHz,
3.2 GB/s transfer rate)
4 onboard RIMM sockets
supporting RDRAM memory.
rate)
3 System Board
System Bus
71