Accelerated Graphics Port (Agp) Controller - HP P Class 450/500/550/600/650/700/750 Reference Manual

System Board

Accelerated Graphics Port (AGP) Controller

Accelerated Graphics Port (AGP) Controller
The AGP technology was developed as a means to access system memory as a viable
alternative to augmenting the memory of the graphics subsystem to meet the needs of high
quality 3D graphics applications. All models of HP V
support an AGP (Accelerated Graphics Port) device.
The AGP bus is based upon a 66 MHz, 32 Bit PCI bus architecture, to which several signal
groups have been added. These additional signals make it possible to implement the
following AGP-specific control and transfer mechanisms:
• Pipelining and sideband addressing. These control mechanisms increase the bus
efficiency in relation to the PCI protocol.
• Double clocking (2x mode). This is a transfer mechanism that doubles the peak transfer
rate to 528 MB/s, as two 32-Bit words are transferred in each clock period (2 x 32 bits x
66 MHz).
AGP specific transactions always use pipelining. The other two mechanisms can combine
independently to pipelining, which leads to the following operating modes:
• FRAME based AGP. Only the PCI protocol is used: 66 MHz, 32 Bits, 3.3V, 264 MB/s
peak transfer rate.
• 1 X AGP with pipelining, sideband addressing can be added: 66 MHz, 32 Bits, 3.3V,
increased bus efficiency, 264 MB/s peak transfer rate.
• 2 X AGP with pipelining, sideband addressing can be added: 66 MHz double clocked, 32
Bits, 3.3V, increased bus efficiency, 528 MB/s peak transfer rate.
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