Channel Connections - Texas Instruments ADS7066EVM-PDK User Manual

www.ti.com
2.1 Connector for Channels
The ADS7066 device is designed for easy interface to an external, analog single-ended source, or to
GPIOs through a 100-mil header. Connector J5 provides a connection to the device channels.
lists the channel connections. The ADS7066 channel AIN0 has a buffered operational amplifier, TLV9061,
to drive the analog input. This is further explained in
resistor and capacitor filter circuit to condition the analog input, as
configured to demonstrate GPIO functionality. GPIO7 has a resistor and light-emitting diode (LED) to
visibly demonstrate and monitor digital output channel state.
J5 Connector Pin
J5:3 and J5:4; J5:9 and J5:10
2.2 Digital Interface
As noted in Section
computer over the USB. The two devices on the EVM that communicate over SPI are the ADS7066 ADC
(U3) and the electrically erasable programmable read-only memory (EEPROM) (U4). The EEPROM is
preprogrammed with the information required to configure and initialize the ADS7066 platform. Once the
hardware is initialized, the EEPROM is no longer used.
2.3 ADS7066 PAMBoard Interface
The ADS7066 supports the digital SPI and functional modes as detailed in the
Channel, 16-Bit SAR ADC With GPIOs Data
logic level and is directly connected to the digital I/O lines of the ADC.
2.4 Power Supplies
The device supports a wide range of operation on its analog supply. The AVDD can operate from 3 V to
5.5 V. The DVDD operates from 1.65 V to 5.5 V, independent of the AVDD supply. A voltage regulator
available on the PAMBoard is used to supply 5V to AVDD, the DVDD is also provided by the PAMBoard
at 3.3V. There is an unpopulated option to use a low-dropout (LDO) regulator, for the TPS78001 for
AVDD. There is an onboard option to use an external power supply for DVDD through J2.
SBAU342A – February 2020 – Revised June 2020
Submit Documentation Feedback
Table 2. Channel Connections
J5:1
J5:2 Single-ended analog input or GPIO for channel 1 of the ADC
J5:5 Single-ended analog input or GPIO for channel 2 of the ADC
J5:6 Single-ended analog input or GPIO for channel 3 of the ADC
J5:7 Single-ended analog input or GPIO for channel 4 of the ADC
J5:8 Single-ended analog input or GPIO for channel 5 of the ADC
J5:11 Single-ended analog input or GPIO for channel 6 of the ADC
J5:12
1, the ADS7066 interfaces with the PAMBoard, which in turn communicates with the
Copyright © 2020, Texas Instruments Incorporated
Section 4. Channels AIN1 through AIN6 have a
Figure 2
Description
Single-ended analog input with buffer
LED GPO for channel 7 of the ADC
EVM ground
Sheet. The PAMBoard is capable of operating at a 3.3-V
ADS7066EVM-PDK Evaluation Module
ADS7066EVM Overview
Table 2
shows. Channel 7 is hardware-
ADS7066 Small, 8-
5