Input Signal-Conditioning Block On The Ads7066Evm; Channel 0 Input Signal Conditioning Block - Texas Instruments ADS7066EVM-PDK User Manual

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Input Signal-Conditioning Block on the ADS7066EVM

For applications where the input signal requires additional conditioning before the ADC input, the
ADS7066EVM has an onboard signal-conditioning path on channel 0. The input signal header, J5 is
connected to the amplifier input, OPA325. By default, this signal-conditioning block is populated on the
evaluation board as a non-inverting buffer using the OPA325 device. The board has a provision to bypass
the operational amplifier (U5) based on the signal conditioning requirement. To bypass this block, remove
the R21 0-Ω resistor and populate R26. See
AIN0
SBAU342A – February 2020 – Revised June 2020
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0
R20
AVDD
±
107
OPA325
+
GND
GND
Figure 19. Channel 0 Input Signal Conditioning Block
Copyright © 2020, Texas Instruments Incorporated
Input Signal-Conditioning Block on the ADS7066EVM
Section 5.3 for more details.
AVDD
5.0 V
ADS7066
ADS7066EVM-PDK Evaluation Module
DVDD
3.3 V
CS
SCLK
Host MCU
SDI
SDO
19