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MCU/A
ARM
/RXD
Figure 21
NOTE
Transistor c
circuit solutio
on is not suit
3.12. PC
CM and I2
2C Interfa
EC25 provid
des one Pu
lse Code M
following mo
odes:
Primary
y mode (sho
ort sync, wor
Auxiliar
ry mode (lon
ng sync, wor
In primary m
mode, the d
ata is samp
edge; the P
CM_SYNC
falling edge
1024 and20
048kHz for d
different spe
In auxiliary
mode, the d
data is samp
edge; while
the PCM_S
SYNC rising
128kHz PC
M_CLK and
d an 8kHz, 5
EC25 supp
orts 8-bit A
A-law andμ-l
theprimary
mode's tim
ming relation
auxiliary mo
ode's timing
relationship
EC25-A_Us
E
All manuals and user guides at all-guides.com
4.7K
VDD_EXT
1nF
/TXD
1nF
10K
VCC_MCU
4.7K
/RTS
/CTS
GPIO
EINT
GPIO
GND
1: Referenc
e Circuit wi
table for hig
h baud rate
ace
odulation (P
PCM) digital
rks as both
master and
rks as maste
er only)
pled on the f
falling edge
represents
the MSB. In
ech codecs
.
pled on the f
falling edge
edge repres
sents the MS
50% duty cyc
cle PCM_SY
aw, and als
so 16-bit lin
nship with 8
8kHz PCM_
p with 8kHz
PCM_SYNC
ser_ManualC
Confidentia
VDD_EXT
Mo
odule
10K
RXD
TXD
VDD_EXT
V
RTS
CTS
DTR
RI
DCD
GND
ith Transist
tor Circuit
s exceeding
g 460Kbps.
interface fo
or audio des
sign, which s
slave)
of the PCM
M_CLK and t
transmitted o
n this mode,
PCM_CLK
supports 12
of the PCM
M_CLK and t
transmitted
SB. In this m
mode, PCM i
nterface ope
YNC only.
near data fo
ormats. The
following f
_SYNC and
d 2048kHz
PCM_CLK,
C and 128kH
Hz PCM_CL
LK.
al / Release
d
38 / 6
69
L
LTE Module
e
EC25-AU
ser Manua
al
supports the
e
on the rising
g
28, 256, 512
2,
on the rising
g
erates with a
a
igures show
w
as well as
s
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