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PCM_OUT
T
25
PCM_SYN
NC
26
PCM_CLK
K
27
I2C_SCL
41
I2C_SDA
42
Clock and m
mode can be
e configured
short sync d
data format w
with 2048kH
command A
AT+QDAI for
r details.
The followin
ng figure sho
ows the refe
PC
CM_CLK
PCM
M_SYNC
PC
M_OUT
PCM_IN
P
I2
2C_SCL
I2
2C_SDA
Modul
le
Figure
e 24: Refere
NOTES
1.
It is re
ecommended
d to reserve
PCM_C
CLK.
2.
EC25 w
works as a m
master devic
E
EC25-A_Us
All manuals and user guides at all-guides.com
DO
PCM d
ata output
IO
PCM d
ata frame sy
IO
PCM d
ata bit clock
OD
I2C ser
rial clock
OD
I2C ser
rial data
d by AT com
mmand, and
HzPCM_CLK
K and 8kHz
erence desig
gn of PCM in
BCLK
LRCK
DAC
ADC
SCL
SDA
1.8V
ence Circui
t of PCM A
e RC (R=2
2ohm, C=2
ce pertaining
g to I2C inte
ser_ManualC
Confidentia
1.8V powe
er domain
ync signal
1.8V powe
er domain
k
1.8V powe
er domain
Require e
external pull-
Require e
external pull-
the default
configuratio
on is master
PCM_SYNC
C. Refer to d
document [
nterface with
h external co
odec IC.
MI
CBIAS
INP
INN
LOUTP
L
LOUTN
Codec
pplication w
with Audio
Codec
2pF) circuit
t on the PC
CM lines, e
rface.
al / Release
d
40 / 6
69
LTE Module
L
e
EC25-AU
ser Manua
al
-up to 1.8V
-up to 1.8V
mode using
g
[2] about the
e
specially fo
r
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