NXP Semiconductors MPC5566 Reference Manual

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MPC5566 Microcontroller

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MPC5566 Reference Manual Addendum, Rev 2

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MPC5566 Microcontroller Reference Manual, Rev 2

MPC5566RM

Rev. 2.1, 05/2012

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Page 1 Freescale Semiconductor MPC5566RM Rev. 2.1, 05/2012 MPC5566 Microcontroller Reference Manual This MPC5566 Reference Manual set consists of the following files: • MPC5566 Reference Manual Addendum, Rev 2 • MPC5566 Microcontroller Reference Manual, Rev 2 © Freescale Semiconductor, Inc., 2012. All rights reserved.
Page 2: Mpc5566 Reference Manual,
MPC5566RM. For convenience, the addenda items are grouped by revision. Please check our website http://www.freescale.com/powerarchitecture for the latest updates. The current version available of the MPC5566 Microcontroller Reference Manual is Revision 2.0. © Freescale Semiconductor, Inc., 2009–2012. All rights reserved.
Page 3 Data Register Empty and LIN Transmit Data Ready DMA requests eSCIB_COMBTX ESCIB.SR[TDRE] || eSCIB combined DMA ESCIB.SR[TC] || request of the Transmit ESCIB.SR[TXRDY] Data Register Empty and LIN Transmit Data Ready DMA requests MPC5566 Reference Manual Addendum, Rev. 2 Freescale Semiconductor...
Page 4: Mpc5566 Reference Manual Addendum, Rev
Peripheral bridge A off-platform PBRIDGE_A_OPACR1 32-bit Base + 0x0044 peripheral access control register 1 Peripheral bridge A off-platform PBRIDGE_A_OPACR2 32-bit Base + 0x0048 peripheral access control register 2 Reserved — — Base + (0x004C- 0xC3F7_FFFF) MPC5566 Reference Manual Addendum, Rev. 2 Freescale Semiconductor...
Page 5 Peripheral bridge B off-platform PBRIDGE_B_OPACR2 32-bit Base + 0x0048 peripheral access control register 2 Peripheral bridge B off-platform PBRIDGE_B_OPACR3 32-bit Base + 0x004C peripheral access control register 3 Reserved — — (Base + 0x0050)- 0xFFF0_3FFF) MPC5566 Reference Manual Addendum, Rev. 2 Freescale Semiconductor...
Page 6 • Bit 22-23–TRIGSELC: Correct the input select description as follows: 00: Replace the term “Invalid value” with “No Trigger” • Bit 30-31–TRIGSELD: Correct the input select description as follows: 00: Replace the term “Invalid value” with “No Trigger” MPC5566 Reference Manual Addendum, Rev. 2 Freescale Semiconductor...
Page 7 INTC as an interrupt event setting the flag bit. MPC5566 Reference Manual Addendum, Rev. 2 Freescale Semiconductor...
Page 8: Table Of Contents
INTC_CPR Read INTC_IACKR Write INTC_EOIR INTVEC in INTC_IACKR PRI in INTC_CPR Last In / First Out Entry in LIFO Peripheral Interrupt Request 100 Peripheral Interrupt Request 200 Raised Priority Preserved Timing Diagram MPC5566 Reference Manual Addendum, Rev. 2 Freescale Semiconductor...
Page 9 “To use the 8–20 MHz OSC, the PLL predivider must be configured for divide-by-two operation (FMPLL_SYNCR)” by tying PLLCFG[2] low (set PREDIV to 0b000).” Revision history Table 2 provides a revision history for this document. MPC5566 Reference Manual Addendum, Rev. 2 Freescale Semiconductor...
Page 10 • Clarified note in the INTC Interrupt Acknowledge Register • Added a note in the INTC Memory Map table • Clarified note at the end of the MPC5566 Interrupt Request Sources table • Added a paragraph to the Section 10.4.2.1.4, “Priority Comparator Submodule”...
Page 11 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany...
Page 12 MPC5566 Microcontroller Reference Manual Devices Supported: MPC5566 MPC5566 RM Rev. 2.0 23 Apr 2008...
Page 13 Fax: 303-675-2150 Freescale™ and the Freescale logo are trademarks of Freescale LDCForFreescaleSemiconductor@hibbertgroup.com Semiconductor, Inc. All other product or service names are the property of their respective owners.© Freescale Semiconductor, Inc. 2008. All rights reserved. MPC5566 RM Rev. 2.0 23 Apr 2008...
Page 14 RSTOUT ........... . . 2-19 2.3.1.3 Phase Locked-Loop Configuration / External Interrupt Request / GPIO MPC5566 Reference Manual, Rev. 2 Freescale Semiconductor...
Page 15 DATA[25]_FEC_RX_DV_GPIO[53] ....... 2-22 2.3.2.17 External Data / Ethernet Transmit Enable / GPIO MPC5566 Reference Manual, Rev. 2 Freescale Semiconductor...
Page 16 MDO[3:1] ........... . 2-25 2.3.3.6 Nexus Message Data Out / GPIO MPC5566 Reference Manual, Rev. 2 Freescale Semiconductor...
Page 17 SINA_PCSC[2]_GPIO[94] ........2-27 MPC5566 Reference Manual, Rev. 2...
Page 18 AN[5]_DAN2– ..........2-31 MPC5566 Reference Manual, Rev. 2...
Page 19 ETPUA[5]_ETPUA[17]_GPIO[119] ....... 2-34 MPC5566 Reference Manual, Rev. 2 Freescale Semiconductor...
Page 20 ETPUA[30]_PCSC[3]_GPIO[144] ....... . . 2-37 2.3.9.30 eTPU A Channel / DSPI C / GPIO MPC5566 Reference Manual, Rev. 2 Freescale Semiconductor...
Page 21 GPIO[206:207] ..........2-40 MPC5566 Reference Manual, Rev. 2...
Page 22 VPP ............2-43 MPC5566 Reference Manual, Rev. 2...
Page 23 3.3.1.3 Effective to Real Address Translation ....... 3-16 MPC5566 Reference Manual, Rev. 2...
Page 24 4.4.2.3.3Loss-of-Lock Reset ........4-8 MPC5566 Reference Manual, Rev. 2...
Page 25 Overview ............6-3 MPC5566 Reference Manual, Rev. 2...
Page 26 6.3.1.29 Pad Configuration Registers 53 (SIU_PCR53) ..... . . 6-33 6.3.1.30 Pad Configuration Registers 54 (SIU_PCR54) ..... . . 6-34 MPC5566 Reference Manual, Rev. 2 Freescale Semiconductor...
Page 27 6.3.1.74 Pad Configuration Register 108 (SIU_PCR108) ..... . 6-61 6.3.1.75 Pad Configuration Register 109 (SIU_PCR109) ..... . 6-62 MPC5566 Reference Manual, Rev. 2 Freescale Semiconductor...
Page 28 6.3.1.119 Pad Configuration Registers 211–212 (SIU_PCR211–SIU_PCR212) ..6-91 6.3.1.120 Pad Configuration Register 213 (SIU_PCR213) ..... 6-91 MPC5566 Reference Manual, Rev. 2 Freescale Semiconductor...
Page 29 6.3.1.164 Chip Configuration Register (SIU_CCR) ......6-115 6.3.1.165 External Clock Control Register (SIU_ECCR) ..... 6-116 MPC5566 Reference Manual, Rev. 2 xviii...
Page 30 Introduction ..............8-1 MPC5566 Reference Manual, Rev. 2...
Page 31 9.2.2.12 eDMA Clear DONE Status Bit Register (EDMA_CDSBR) ... . . 9-18 9.2.2.13 eDMA Interrupt Request Registers (EDMA_IRQRH, EDMA_IRQRL) . . . 9-19 MPC5566 Reference Manual, Rev. 2 Freescale Semiconductor...
Page 32 10.3.1.3 INTC Interrupt Acknowledge Register (INTC_IACKR) ....10-11 10.3.1.4 INTC End-of-Interrupt Register (INTC_EOIR) ..... 10-13 MPC5566 Reference Manual, Rev. 2 Freescale Semiconductor...
Page 33 Block Diagrams ........... . 11-1 MPC5566 Reference Manual, Rev. 2...
Page 34 11.4.3.3 FM Calibration Routine ........11-29 MPC5566 Reference Manual, Rev. 2...
Page 35 12.4 Functional Description ............12-21 MPC5566 Reference Manual, Rev. 2...
Page 36 12.4.2.10.1Address Decoding for External Master Accesses ... . 12-60 12.4.2.10.2Bus Transfers Initiated by an External Master ....12-61 MPC5566 Reference Manual, Rev. 2 Freescale Semiconductor...
Page 37 13.4.1.4 Flash Read Cycles—Buffer Hit ........13-23 MPC5566 Reference Manual, Rev. 2...
Page 38 15.2 Modes of Operation ............15-4 MPC5566 Reference Manual, Rev. 2...
Page 39 FEC Frame Reception ..........15-35 MPC5566 Reference Manual, Rev. 2...
Page 40 16.3.2.2.1External Boot MMU Configuration ......16-8 16.3.2.2.2Single Bus Master or Multiple Bus Masters ....16-9 MPC5566 Reference Manual, Rev. 2 Freescale Semiconductor...
Page 41 17.4.4.4 Unified Channel Operating Modes ....... 17-28 17.4.4.4.1General Purpose Input/Output Mode (GPIO) ....17-29 MPC5566 Reference Manual, Rev. 2 Freescale Semiconductor...
Page 42 User Mode ............18-11 MPC5566 Reference Manual, Rev. 2...
Page 43 Overview ............19-2 MPC5566 Reference Manual, Rev. 2...
Page 44 19.4.3.1 CFIFO Basic Functionality ........19-59 MPC5566 Reference Manual, Rev. 2...
Page 45 19.5.2.1 Command Queue/CFIFO Transfers ......19-112 MPC5566 Reference Manual, Rev. 2...
Page 46 20.3.2.8 DSPI Transmit FIFO Registers 0–3 (DSPIx_TXFRn) ....20-26 20.3.2.9 DSPI Receive FIFO Registers 0–3 (DSPIx_RXFRn) ....20-27 MPC5566 Reference Manual, Rev. 2 Freescale Semiconductor...
Page 47 DSPI Baud Rate and Clock Delay Generation ......20-53 MPC5566 Reference Manual, Rev. 2...
Page 48 21.2 External Signal Description ........... . 21-3 MPC5566 Reference Manual, Rev. 2...
Page 49 21.4.10.1 Features of the LIN Hardware ........21-36 MPC5566 Reference Manual, Rev. 2...
Page 50 22.4.2.1 Arbitration Process ......... . . 22-25 MPC5566 Reference Manual, Rev. 2...
Page 51 23.5.3.4 Pin Values after POR Negates ........23-7 MPC5566 Reference Manual, Rev. 2...
Page 52 25.1.3.3 Reduced-Port Mode ..........25-5 MPC5566 Reference Manual, Rev. 2...
Page 53 25.7.2.6 MCKO ........... . . 25-24 MPC5566 Reference Manual, Rev. 2...
Page 54 25.13.3 Program Trace Synchronization Messages ......25-53 MPC5566 Reference Manual, Rev. 2...
Page 55 25.15.2 Features ............25-74 MPC5566 Reference Manual, Rev. 2...
Page 56 A.2 MPC5566 Register Map ........
Page 57 B.3 Device-Specific Information ........... . B-4 B.3.1 MPC5566 Calibration Bus Implementation ....... . . B-4 B.4 Signals and Pads .
Page 58: Mpc5566 Microcontroller Reference Manual, Rev
Introduction Overview The MPC5566 microcontroller (MCU) is a member of the MPC5500 family of next generation powertrain microcontrollers built on Power Architecture™ technology. The MPC5500 family contains a host processor core that complies with the Power Architecture embedded category, which is 100 percent user mode compatible with the original Power PC™...
Page 59: Rev.
MII signals. The upper 16-bits of the 32-bit external bus interface (EBI) are used to connect to an external Ethernet device. The FEC contains built-in transmit and receive message FIFOs and DMA support. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 60: Rev.
Introduction Block Diagram Figure 1-1 is a block diagram of the MPC5566. e200z6 Core Core registers Master Slave GPRs (64 bits) Internal Integer Master Slave SPRs SRAM execution unit 128 KB Unified Master Slave 32-KB Flash Multiply cache 3 MB...
Page 61: Features
Introduction Features This section provides a high-level description of the features found in the MPC5566. • Operating parameters — Fully static operation, up to 144 MHz — –40 to 150 °C junction temperature — Low-power design – Less than 1.2 Watts power dissipation –...
Page 62 – Conversion instructions between single precision floating point and fixed point — Long cycle time instructions, except for guarded loads. Do not increase interrupt latency in the MPC5566 to reduce latency; long cycle time instructions are aborted upon interrupt requests. — Extensive system development support through Nexus debug module •...
Page 63 • System integration unit (SIU) – Centralized GPIO control of bus pins: 416 BGA package: 178 pins – 416 CSP BGA package: 225 pins — Centralized pad control on a per-pin basis MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 64 — Four selectable time bases plus a shared time or angle counter bus — DMA and interrupt request support — Motor control capability • Enhanced time processor units (eTPUs) — Two 32-channel engines MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 65 Two enhanced serial communication interface (eSCI) modules — UART mode provides NRZ format and half or full duplex interface — eSCI bit rate up to 1 Mb/sec. — Advanced error detection, and optional parity generation and detection MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 66 — Three test data registers: a bypass register, a boundary scan register, and a device identification register — TAP controller state machine that controls the operation of the data registers, instruction register and associated circuitry MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 67 — Address recognition for broadcast, single-station address, promiscuous mode, and multicast hashing — Ethernet channel uses DMA burst transactions to transfer data to and from external/system memory MPC5566 Microcontroller Reference Manual, Rev. 2 1-10 Freescale Semiconductor...
Page 68: Mpc5500 Family Comparison
Introduction MPC5500 Family Comparison The following table compares the product features of the MPC5554 versus the MPC5566: Table 1-1. MPC5554 and MPC5566 Comparison Module MPC5554 MPC5566 PowerPC core e200z6 e200z6 Variable Length Encoding (VLE) — Unified cache (KB) Memory management unit (MMU)
Page 69: Detailed Features
Introduction Table 1-1. MPC5554 and MPC5566 Comparison (continued) Module MPC5554 MPC5566 Enhanced Time Processing Unit (eTPU) 64 channels 64 channels eTPU A eTPU B Code memory (KB) Parameter RAM (KB) Nexus Class 3 Class 3 Interrupt controller (INT) Enhanced queued analog-to-digital converter (eQADC)
Page 70 32-bits and the normal integer type. Low latency fixed-point and floating-point add, subtract, multiply, divide, compare, and conversion operations are provided, and most operations can be pipelined. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 1-13...
Page 71: System Bus Crossbar Switch (Xbar)
1. Although this device has a maximum of 329 interrupts, the logic requires that the total number of interrupts be divisible by four. Therefore, the total number of interrupts specified for this device is 332. MPC5566 Microcontroller Reference Manual, Rev. 2 1-14...
Page 72: Frequency Modulated Phase-Locking Loop (Fmpll)
The error correction status module (ECSM) provides status information regarding platform memory errors reported by error-correcting codes. 1.5.9 Flash Memory The MPC5566 provides 3 MB of programmable, non-volatile, flash memory storage. Non-volatile memory (NVM) can be used for instruction and/or data storage. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 73: Cache
• Booting from internal flash memory • Single master booting from external memory • Serial boot loading (program is downloaded to SRAM over an eSCI or FlexCAN peripheral and then executed) MPC5566 Microcontroller Reference Manual, Rev. 2 1-16 Freescale Semiconductor...
Page 74: Enhanced Management Input/Output System (Emios)
RAM to form a powerful time processing subsystem. The MPC5566 has two eTPU engines. You can use the high-level assembler and compiler, along with the eTPU documentation set, to develop customized eTPU functions. The eTPU supports several features of older TPU versions, making it easy to port earlier application versions.
Page 75: Enhanced Serial Communications Interface (Esci)
The channels and register content are transmitted using a SPI-like protocol. The MPC5566 has four DSPI modules (A, B, C, and D). The DSPIs have three configurations: • Serial peripheral interface (SPI) configuration where the DSPIs operate as serial ports only with support for queues.
Page 76: Fast Ethernet Controller (Fec)
The JTAGC module is compliant with the IEEE® 1149.1-2001 standard. 1.5.21 Fast Ethernet Controller (FEC) The MPC5566 fast Ethernet controller includes these distinctive features: • IEEE 802.3 MAC (compliant with IEEE 802.3 1998 edition) •...
Page 77: Mpc5500 Family Memory Map
4 KB boundary. Peripheral modules may be redundantly mapped. You must use the MMU to prevent corruption. Table 1-2 shows a detailed list of the device memory map. Table 1-2. MPC5566 Detailed Memory Map Allocated Size Used Size Address Range...
Page 78 Introduction Table 1-2. MPC5566 Detailed Memory Map (continued) Allocated Size Used Size Address Range (bytes) (bytes) 0xC3FA_0000–0xC3FA_3FFF 16 KB 1056 Modular timer system (eMIOS) 0xC3FA_4000–0xC3FB_FFFF 112 KB Reserved 0xC3FC_0000–0xC3FC_3FFF 16 KB 3 KB Enhanced time processing unit (eTPU) registers 0xC3FC_4000–0xC3FC_7FFF...
Page 79: Multi-Master Operation Memory Map
Introduction Table 1-2. MPC5566 Detailed Memory Map (continued) Allocated Size Used Size Address Range (bytes) (bytes) 0xFFFC_0000–0xFFFC_3FFF 16 KB 1152 Controller area network (FlexCAN A) 0xFFFC_4000–0xFFFC_7FFF 16 KB 1152 Controller area network (FlexCAN B) 0xFFFC_8000–0xFFFC_BFFF 16 KB 1152 Controller area network (FlexCAN C) 0xFFFC_C000–0xFFFC_FFFF...
Page 80 MCU acting as a slave in a multi-master system from the point of view of the external master. Table 1-4. MPC5566 Family Slave Memory Map as Seen from an External Master External Address Range...
Page 81 Introduction MPC5566 Microcontroller Reference Manual, Rev. 2 1-24 Freescale Semiconductor...
Page 82: Block Diagram
Read the last two columns in Table 2-1 for a list of BGA package connections provided by the VertiCal assembly. NOTE The Vertical assembly has ball connections for all the available signals on the device. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 83 DDA0 DAN3+_AN[6] SSA0 DAN3–_AN[7] DDA1 ANW_AN[8] SSA1 ANX_AN[9] DDSYN eQADC ANY_AN[10] POWER/ SSSYN GROUND ANZ_AN[11] FLASH SDS_MA[0]_AN[12] SDO_MA[1]_AN[13] STBY SDI_MA[2]_AN[14] FCK_AN[15] AN[16:39] DDEH GPIO[111:112]_ETRIG[0:1] DD33 REFBYPC NO CONNECT Figure 2-1. MPC5566 Signals MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 84: External Signal Descriptions
The PA field is from 1- to 3-bits wide, depending on the PCR register. Figure 2-3 explains the symbol definitions used in the P/A/G column for Table 2-1. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 85: Device Signals Summary
/ – RSTCFG_ Reset configuration input RSTCFG / – / Up DDEH6 GPIO[210] GPIO BOOTCFG[0]_ Boot configuration input BOOTCFG IRQ[2]_ External interrupt request – / Down AA25 AB26 DDEH6 / Down GPIO[211] GPIO MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 86 Signal Description Table 2-1. MPC5566 Signal Properties (continued) Status After Vertical During Signal Names Signal Functions Type Voltage Type Reset Package Assembly Reset BOOTCFG[1]_ Boot configuration input BOOTCFG IRQ[3]_ External interrupt request – / Down AB24 DDEH6 / Down GPIO[212]...
Page 87 Signal Description Table 2-1. MPC5566 Signal Properties (continued) Status After Vertical During Signal Names Signal Functions Type Voltage Type Reset Package Assembly Reset DATA[18]_ External data bus FEC_TX_ER_ Ethernet transmit error – / Up – / Up DDE3 GPIO[46] GPIO...
Page 88: Cal_Addr[8]_Cal_Cs
Signal Description Table 2-1. MPC5566 Signal Properties (continued) Status After Vertical During Signal Names Signal Functions Type Voltage Type Reset Package Assembly Reset BDIP_ External burst data in progress – / Up – / Up DDE2 GPIO[63] GPIO WE/BE[0:1]_ External write/byte enable –...
Page 89: Cal_Ts
Signal Description Table 2-1. MPC5566 Signal Properties (continued) Status After Vertical During Signal Names Signal Functions Type Voltage Type Reset Package Assembly Reset CAL_TS Calibration transfer start – / Up – / Up — AA11 DDE12 NEXUS EVTI Nexus event in...
Page 90 Signal Description Table 2-1. MPC5566 Signal Properties (continued) Status After Vertical During Signal Names Signal Functions Type Voltage Type Reset Package Assembly Reset CNTXC_ FlexCAN C transmit PCSD[3]_ DSPI D peripheral chip select – / Up – / Up DDEH6...
Page 91 Signal Description Table 2-1. MPC5566 Signal Properties (continued) Status After Vertical During Signal Names Signal Functions Type Voltage Type Reset Package Assembly Reset SCKB_ DSPI B clock PCSC[1]_ DSPI C peripheral chip select – / Up – / Up DDEH10...
Page 92 Signal Description Table 2-1. MPC5566 Signal Properties (continued) Status After Vertical During Signal Names Signal Functions Type Voltage Type Reset Package Assembly Reset AN[8]_ Single-ended analog input I / – AN[8] / – DDA1 External multiplexed analog input AN[9]_ Single-ended analog input I / –...
Page 93 Signal Description Table 2-1. MPC5566 Signal Properties (continued) Status After Vertical During Signal Names Signal Functions Type Voltage Type Reset Package Assembly Reset Voltage reference low – / – – SSINT REFBYPC Reference bypass capacitor input – – / –...
Page 94 Signal Description Table 2-1. MPC5566 Signal Properties (continued) Status After Vertical During Signal Names Signal Functions Type Voltage Type Reset Package Assembly Reset ETPUA[29]_ eTPU A channel (output only) – / – / PCSC[2]_ DSPI C peripheral chip select DDEH1...
Page 95 Signal Description Table 2-1. MPC5566 Signal Properties (continued) Status After Vertical During Signal Names Signal Functions Type Voltage Type Reset Package Assembly Reset EMIOS[8:9]_ eMIOS channel – / – / AC17, ETPUA[8:9]_ eTPU A channel (output only) N21, AD23 DDEH4...
Page 96 Signal Description Table 2-1. MPC5566 Signal Properties (continued) Status After Vertical During Signal Names Signal Functions Type Voltage Type Reset Package Assembly Reset GPIO EMIOS[14:15]_ eMIOS channel (output only) – / Up – / Up H24, G25 J26, H27 DDEH6...
Page 97 Signal Description Table 2-1. MPC5566 Signal Properties (continued) Status After Vertical During Signal Names Signal Functions Type Voltage Type Reset Package Assembly Reset M10, M11, N10, N11, P10, P11, R10, R11, T1, T4, M11, N11, T10, T12, N12, N13, T13, T14, External I/O supply input 1.8–3.3 V...
Page 98 AF24, AG25 For each pin in the table, each line in a Function row is a separate function of the pin. For all MPC5566 I/O pins the selection of primary pin function or secondary function or GPIO is done in the MPC5566 SIU except where explicitly noted.
Page 99: Detailed Signal Description
The pins are reserved for the clock and inverted clock outputs for DDR memory interface. Detailed Signal Description This section gives detailed descriptions of the device signals. Read Section 2.2.2, “Device Signals Summary,” for the signal properties. MPC5566 Microcontroller Reference Manual, Rev. 2 2-18 Freescale Semiconductor...
Page 100: Reset And Configuration Signals
The alternate function is an external interrupt request input, and the second alternate function is the data output for the DSPI module D. 2.3.1.5 Phase Locked-Loop Configuration PLLCFG[2] The MPC5566 does not use PLLCFG[2], therefore PLLCFG[2] is tied low. Read Section 11.3.1.1, “Synthesizer Control Register (FMPLL_SYNCR).” MPC5566 Microcontroller Reference Manual, Rev. 2...
Page 101: Rstcfg_Gpio[210]
ADDR[9:11] and is an external bus address function. 2.3.2.3 External Address / GPIO ADDR[8:11]_GPIO[4:7] ADDR[8:11]_GPIO[4:7] are the External Bus Interface (EBI) address signals. 2.3.2.4 External Address / GPIO ADDR[12:29]_GPIO[8:25] ADDR[12:29]_GPIO[8:25] are External Bus Interface (EBI) address signals. MPC5566 Microcontroller Reference Manual, Rev. 2 2-20 Freescale Semiconductor...
Page 102: External Address / Master Address Expansion / Gpio Addr[30:31]_Addr[6:7]_Gpio[26:27]
DATA[20]_FEC_TXD[0]_GPIO[48] is an EBI data signal. The alternate signal is FEC transmit data [0] function. 2.3.2.12 External Data / Ethernet Receive Error / GPIO DATA[21]_FEC_RX_ER_GPIO[49] DATA[21]_FEC_RX_ER_GPIO[49] is an EBI data signal. The alternate function is FEC receive error function. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 2-21...
Page 103: Data[22]_Fec_Rxd[0]_Gpio[50]
DATA[28]_FEC_TXD[1]_GPIO[56] is an EBI data signal. The alternate function is FEC transmit data [1]. 2.3.2.20 External Data / Ethernet Receive Data / GPIO DATA[29]_FEC_RXD[1]_GPIO[57] DATA[29]_FEC_RXD[1]_GPIO[57] is an EBI data signal.The alternate function is FEC receive data [1]. MPC5566 Microcontroller Reference Manual, Rev. 2 2-22 Freescale Semiconductor...
Page 104: Data[30]_Fec_Rxd[2]_Gpio[58]
TS_GPIO[69] is asserted by the EBI owner to indicate the start of a transfer. 2.3.2.29 External Transfer Acknowledge / GPIO TA_GPIO[70] TA_GPIO[70] is asserted by the EBI owner to acknowledge that the slave has completed the current transfer. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 2-23...
Page 105: Tea_Fec_Rxd[3]_Gpio[71]
EVTO is an output that provides timing to a development tool for a single watchpoint or breakpoint occurrence. 2.3.3.3 Nexus Message Clock Out MCKO MCKO is a free running clock output to the development tools which is used for timing of the MDO and MSEO signals. MPC5566 Microcontroller Reference Manual, Rev. 2 2-24 Freescale Semiconductor...
Page 106: Mdo[0]
TDI provides the serial test instruction and data input for the on-chip test logic. 2.3.4.3 JTAG Test Data Output TDO provides the serial test data output for the on-chip test logic. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 2-25...
Page 107: Cntxa_Txda_Gpio
CAN C Transmit / DSPI D / GPIO CNTXC_PCSD[3]_GPIO[87] CNTXC_PCSD[3]_GPIO[87] is the transmit pin for the FlexCAN C module. The alternate function is PCSD[3], a peripheral chip select for the DSPI D module. MPC5566 Microcontroller Reference Manual, Rev. 2 2-26 Freescale Semiconductor...
Page 108: Cnrxc_Pcsd[4]_Gpio[88
SINA_PCSC[2]_GPIO[94] — SINA is the primary function and is the data input pin for the DSPI A module. The alternate signal function is PCSC[2], a peripheral chip select for the DSPI C module. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 109: Souta_Pcsc[5]_Gpio[95
PCSA[5]_PCSB[3]_GPIO[101] — The PCSA[5] is the primary function and is a peripheral chip select output pin for the DSPI A module. The alternate function is PCSB[3], a peripheral chip select output pin for the DSPI B module. MPC5566 Microcontroller Reference Manual, Rev. 2 2-28 Freescale Semiconductor...
Page 110: Sckb_Pcsc[1]_Gpio[102
PCSB[3]_SINC_GPIO[108] — PCSB[3] is the primary function and is a peripheral chip select output pin for the DSPI B module. SINC is the alternate function and is the data input for the DSPI C module. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 111: Pcsb[4]_Sckc_Gpio[109
Analog Input / Differential Analog Input AN[4]_DAN2+ AN[4] is a single-ended analog input to the two on-chip ADCs. DAN2+ is the positive terminal of the differential analog input DAN2 (DAN2+ to DAN2–). MPC5566 Microcontroller Reference Manual, Rev. 2 2-30 Freescale Semiconductor...
Page 112: An[5]_Dan2–
AN[11] is an analog input pin. ANZ is an analog input in external multiplexed mode. NOTE Attempts to convert the input voltage applied to AN[12], AN[13], AN[14], and AN[15] while a non-eQADC function is selected causes an undefined conversion result. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 2-31...
Page 113: An[12]_Ma[0]_Sds
AN[15]_FCK is an analog input pin. The alternate function is the free running clock for the eQADC SSI. This pin has reduced analog to digital conversion accuracy as compared to the AN[0:7] and AN[16:39] analog input pins. This pin is configured by setting the pad configuration register, SIU_PCR218. MPC5566 Microcontroller Reference Manual, Rev. 2 2-32 Freescale Semiconductor...
Page 114: Tcrclka_Irq[7]_Gpio[113
A TCR Clock / External Interrupt Request / GPIO TCRCLKA_IRQ[7]_GPIO[113] TCRCLKA_IRQ[7]_GPIO[113] is the TCR clock input for the eTPU A module. The alternate function is an external interrupt request input for the SIU module. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 2-33...
Page 115: Etpua[0]_Etpua[12]_Gpio[114]
ETPUA[5]_ETPUA[17]_GPIO[119] is an input/output channel pin for the eTPU A module. The alternate function, ETPUA[17], is an output channel for the eTPU A module. When configured as ETPUA[17], the pin functions as output only. MPC5566 Microcontroller Reference Manual, Rev. 2 2-34 Freescale Semiconductor...
Page 116: Etpua[12:15]_Pcsb[1:5]_Gpio[126:129]
A Channel / DSPI B / GPIO ETPUA[12]_PCSB[1]_GPIO[126] ETPUA[12]_PCSB[1]_GPIO[126] is an input/output channel pin for the eTPU A module. The alternate function is a peripheral chip select for the DSPI B module. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 2-35...
Page 117: Etpua[16:19]_Pcsd[1:4]_Gpio[130:133]
A Channel / External Interrupt / GPIO ETPUA[20]_IRQ[8]_GPIO[134] ETPUA[20]_IRQ[8]_GPIO[134] is an input/output channel pin for the eTPU A module. The alternate function is an external interrupt request input for the SIU module. MPC5566 Microcontroller Reference Manual, Rev. 2 2-36 Freescale Semiconductor...
Page 118: Etpua[24:27]_Irq[12:15]_Gpio[138:141]
A Channel / DSPI C / GPIO ETPUA[31]_PCSC[4]_GPIO[145] ETPUA[31]_PCSC[4]_GPIO[145] is an input/output channel pin for the eTPU A module. The alternate function is a peripheral chip select for the DSPI C module. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 2-37...
Page 119: Tcrclkb_Irq[6]_Gpio[146
Output Channel / DSPI C / GPIO EMIOS[12]_SOUTC_GPIO[191] EMIOS[12]_SOUTC_GPIO[191] is an output channel pin for the eMIOS module. The alternate function is the data output signal for the DSPI C module. MPC5566 Microcontroller Reference Manual, Rev. 2 2-38 Freescale Semiconductor...
Page 120: Emios[13]_Soutd_Gpio[192
ETPU B (output only). 2.3.10.10 eMIOS Channel / eTPU B Output Channel / GPIO EMIOS[19]_ETPUB[3]_GPIO[198] EMIOS[19]_ETPUB[3]_GPIO[198] is an input/output channel pin for the eMIOS module. The alternate function is an ETPU B output channel. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 2-39...
Page 121: Emios Channel /Etpu B Output Channel / Gpio Emios[20:21]_Etpub[4:5]_Gpio[199:200]
(DDRAM) interface support. The pad types for GPIO[206:207] is F (1.62–3.6 V). Read Section 6.3.1.115, “Pad Configuration Registers 206–207 (SIU_PCR206–SIU_PCR207).” The GPIO[206:207] pins can be selected as sources for the ADC trigger in the SIU_ETISR. MPC5566 Microcontroller Reference Manual, Rev. 2 2-40 Freescale Semiconductor...
Page 122: Calibration Bus Signals
496 pin assembly. 2.3.12.7 Calibration Output Enable CAL_OE CAL_OE is the primary function and is a calibration output enable. It is functional only when using the 496 pin assembly. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 2-41...
Page 123: Xtal
1.5 V regulator control circuit. RCVSS 2.3.14.3 Voltage Regulator Control Output RCCTL is the output pin for the on-chip 1.5 V regulator control circuit. RCCTL MPC5566 Microcontroller Reference Manual, Rev. 2 2-42 Freescale Semiconductor...
Page 124: Vddan
2.3.14.11 Internal Logic Supply Input is the 1.5 V logic supply input. 2.3.14.12 External I/O Supply Input DDEn is the 1.8–3.3 V, with a tolerance of ±10% external I/O supply input. DDEn MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 2-43...
Page 125: Clkout Engclk
The power/ground segmentation applies regardless of whether a particular pin is configured for its primary function or GPIO. Table 2-2. MPC5566 Device Power/Ground Segmentation Voltage Power Segment...
Page 126 +5% to –10%. DDSYN DDA1 During read operations, VPP can be as high as 5.3 V and as low as 3.0 V. Table 2-3. MPC5566 Device Power/Ground Segmentation for the 496 Pin Assembly Power Voltage I/O Pins Powered by Segment...
Page 127 Signal Description Table 2-3. MPC5566 Device Power/Ground Segmentation for the 496 Pin Assembly (continued) Power Voltage I/O Pins Powered by Segment Segment Range 1.8–3.3 V CLKOUT, ENGCLK DDE5 EVTI, EVTO, MCKO, MDO[3:0], MDO[11:4]_GPIO[82:75], MSEO[1:0], RDY, TCK, TDI, TDO, 1.8–3.3 V...
Page 128: Etpu Pin Connections And Serialization
• • • IN 4 IN 13 IN 14 IN 3 DSPI C Figure 2-4. ETPUA[0:15]—DSPI C I/O Connections Table 2-4. ETPUA[0:15]—DSPI C I/O Mapping DSPI C Serialized eTPU A Channel Output Input MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 2-47...
Page 129: Etpua[16:31]
ETPUA[16:23] are also connected to the ETPUA[4:11]_ETPUA[16:23]_GPIO[118:125] pins. eTPU A ETPUA[16]_ CH16 IN GPIO[130] CH16 OUT IN 7 IN 5 DSPI B DSPI D Figure 2-5. ETPUA[16:21]—DSPI B–DSPI D I/O Connections MPC5566 Microcontroller Reference Manual, Rev. 2 2-48 Freescale Semiconductor...
Page 130 14, 15 are connected to eMIOS channels. DSPI B serialized output channels 0 through 7 are not connected. Table 2-6. ETPUA[16:31]—DSPI D I/O Mapping DSPI D Serialized eTPU A Channel Output Inputs MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 2-49...
Page 131: Etpub[0:31]
ETPUB[16:23] channels. The output channels of ETPUB[0:15] are serialized on DSPI A. The full ETPUB to DSPI A connections are given in Table 2-7. MPC5566 Microcontroller Reference Manual, Rev. 2 2-50 Freescale Semiconductor...
Page 132 • • • IN 15 IN 8 IN 7 IN 0 DSPI A Figure 2-7. ETPUB[31:0]—DSPI A I/O Connections Table 2-7. ETPUB[0:15]—DSPI A I/O Mapping DSPI A Serialized eTPU B Channel Output Inputs MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 2-51...
Page 133: Emios Pin Connections And Serialization
EMIOS[10]_ CH10 IN GPIO[189] CH10 OUT CH11 IN EMIOS[11]_ GPIO[190] CH11 OUT IN 1 IN 0 IN 7 IN 6 DSPI B DSPI D Figure 2-8. EMIOS[10:11]—DSPI B–DSPI D I/O Connections MPC5566 Microcontroller Reference Manual, Rev. 2 2-52 Freescale Semiconductor...
Page 134 GPIO[203]_ EMIOS[14] eMIOS CH14 IN EMIOS[14]_ IRQ[0]_ CH14 OUT GPIO[193] CH15 IN EMIOS[15]_ IRQ[1]_ CH15 OUT GPIO[194] GPIO[204]_ OUT 15 OUT 14 EMIOS[15] DSPI D Figure 2-10. EMIOS[14:15]—DSPI D I/O Connections MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 2-53...
Page 135 Signal Description MPC5566 Microcontroller Reference Manual, Rev. 2 2-54 Freescale Semiconductor...
Page 136: Introduction
GPRs defined for integer instructions. Refer to the e200z6 PowerPC Core Reference Manual for more information on the e200z6 core. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 137: Block Diagram
Multiply Instruction Unit Control Unit Instruction Buffer Unified Cache Address 32-KB Data In Branch Data Out Unit Unit Load/ Store Unit Bus Interface Unit Address Data Control Figure 3-1. e200z6 Block Diagram MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 138: Overview
— Minimize power use by the cache by selecting CORG = 1 or by setting WAM = 1. Refer to Table 3-9. • Periodic timer and watchdog functions • Periodic system integrity can be monitored through parallel signature checks MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 139: Instruction Unit Features
Pipelined operation supports throughput of one load or store operation per cycle • Dedicated 64-bit interface to memory supports saving and restoring of up to two registers per cycle for load multiple and store multiple word instructions MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 140: Mmu Features
The integer execution unit consists of a 32-bit arithmetic unit (AU), a logic unit (LU), a 32-bit barrel shifter (shifter), a mask-insertion unit (MIU), a condition register manipulation unit (CRU), a count-leading-zeros unit (CLZ), a 32 x 32 hardware multiplier array, result feed-forward hardware, and support hardware for division. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 141: Core Registers And Programmer's Model
Data is transferred between memory and registers with explicit load and store instructions only. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 142 The number to the right of the special-purpose registers (SPRs) is the decimal number used in the instruction syntax to access the register (for example, the integer exception register (XER) is SPR 1). MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 143 (read-only) L1CSR0 2 - Optional registers defined by the Power SPR 1010 L1CFG0 Architecture embedded category SPR 515 L1FINV0 SPR 1016 3 - Read-only registers Figure 3-2. Supervisor Mode Programmer’s Model MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 144: Power Architecture Registers
Link register (LR). The LR provides the branch target address for the branch conditional to link register (bclr, bclrl) instructions, and is used to hold the address of the instruction that follows a branch and link instruction, typically used for linking to subroutines. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 145: Supervisor-Level Only Registers
— Software-use special purpose registers (SPRGs). The SPRG0–SPRG7 registers are provided for operating system use. — Exception syndrome register (ESR). The ESR register provides a syndrome to differentiate between the different kinds of exceptions which can generate the same interrupt. MPC5566 Microcontroller Reference Manual, Rev. 2 3-10 Freescale Semiconductor...
Page 146 — Timer status register (TSR). This register contains status on timer events and the most recent watchdog timer-initiated processor reset. For more details about these registers, refer to the Power Architecture embedded category specifications. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 3-11...
Page 147: Core-Specific Registers
Debug facility registers — Debug control register 3 (DBCR3) controls for debug functions not described in the Power Architecture embedded category. — Debug counter register (DBCNT) provides counter capability for debug functions. MPC5566 Microcontroller Reference Manual, Rev. 2 3-12 Freescale Semiconductor...
Page 148: E200Z6 Core Complex Features Not Supported In The Device
The OCR[WKUP] bit in the e200z6 OnCE control register (OCR) has no effect. Machine check The machine check input pin is not supported. HID0 [EMCP] has no effect, and MCSR[MCP] always reads a negated value. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 3-13...
Page 149: Functional Description
SIZE[0:3] Page size = 4 KB,16 KB, 64 KB, 256 KB, 1 MB, 4 MB, 16 MB, 64 MB, 256 MB SX, SW, SR Supervisor execute, write, and read permission bits MPC5566 Microcontroller Reference Manual, Rev. 2 3-14 Freescale Semiconductor...
Page 150: Translation Flow
TLB entries. TLB_entry[V] TLB entry Hit TLB_entry[TS] AS (from MSR[IS] or MSR[DS]) Process ID private page shared page TLB_entry[TID] TLB_entry[EPN] EA page number bits Figure 3-4. Virtual Address and TLB-Entry Compare Process MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 3-15...
Page 151: Effective To Real Address Translation
UR—User read permission. Allows loads and load-type cache management instructions to access the page while in user mode. • UW—User write permission. Allows stores and store-type cache management instructions to access the page while in user mode. MPC5566 Microcontroller Reference Manual, Rev. 2 3-16 Freescale Semiconductor...
Page 152: Mmu Assist Registers (Mas[0:4], Mas[6])
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 — TLBSEL — ESEL — Undefined on Power Up ⎯ Unchanged on Reset Reset Figure 3-7. MAS Register 0 Format — MAS[0] MAS[0] fields are defined in Table 3-3. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 3-17...
Page 153: Mas[1] Register
Translation address space. This bit is compared with the IS or DS fields of the MSR (depending on the type of access) to determine if this TLB entry can be used for translation. MPC5566 Microcontroller Reference Manual, Rev. 2 3-18 Freescale Semiconductor...
Page 154: Mas[2] Register
1 This page is considered cache-inhibited. Memory coherence required.The e200z6 does not support the memory coherence required attribute, and thus it is ignored. 0 Memory coherence is not required. 1 Memory coherence is required. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 3-19...
Page 155: Mas[3] Register
16 17 18 19 20 21 22 — TLBSELD — TIDSELD — TSIZED — WD ID MD GD ED Undefined on Power Up ⎯ Unchanged on Reset Reset Figure 3-11. MMU Assist Register 4 MAS[4] MPC5566 Microcontroller Reference Manual, Rev. 2 3-20 Freescale Semiconductor...
Page 156: Mas[6] Register
Table 3-8. MAS[6] — TLB Search Context Register 0 Field Description 0–7 Reserved, must be cleared. 8–15 PID value for searches SPID 16–30 Reserved, must be cleared. AS value for searches MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 3-21...
Page 157: L1 Cache
Control Logic Control Data Array Address/ Processor Interface Tag Array Data Unit Core Data Data Data Path Address Address Address Path Memory Management Unit Figure 3-13. e200z6 Unified Cache Block Diagram MPC5566 Microcontroller Reference Manual, Rev. 2 3-22 Freescale Semiconductor...
Page 158: Cache Organization
(and valid). For invalid lines, the V bit is clear, causing the cache line to be ignored during lookups. Valid lines have their V bit set and D bit cleared, MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 159 • • DW0 DW1 DW2 DW3 Status Set 127 Data or instruction Reference A[0:19] Select HIT 7 HIT 2 Logical OR HIT 1 Comparator HIT 0 Figure 3-15. Cache Lookup Flow MPC5566 Microcontroller Reference Manual, Rev. 2 3-24 Freescale Semiconductor...
Page 160: Cache Line Replacement Algorithm
MMU permissions are set so that no cacheable page has X (execute) permission which also has R (read) or W (write) permission, i.e. can be cacheable and accessed with both instruction and data accesses. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 161: L1 Cache Control And Status Register 0 (L1Csr0)
Bit 3 corresponds to way 3. The WID and WDD bits can be used for locking ways of the cache, and also are used in determining the replacement policy of the cache. MPC5566 Microcontroller Reference Manual, Rev. 2 3-26 Freescale Semiconductor...
Page 162 When set, write accesses are performed in copyback mode unless the “W” page attribute from an optional MMU is set. Disable push buffer 0 = Push buffer enabled 1 = Push buffer disabled MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 3-27...
Page 163 Writing a 0 to this bit while an invalidation operation is in progress will be ignored. Cache invalidation operations require approximately134 cycles to complete. Invalidation occurs regardless of the enable (CE) value. MPC5566 Microcontroller Reference Manual, Rev. 2 3-28 Freescale Semiconductor...
Page 164: L1 Cache Configuration Register 0 (L1Cfg0)
00 - The cache implements a block size of 32 bytes Cache replacement policy 9–10 CREPL 10 - The cache implements a pseudo-round-robin replacement policy Cache locking APU available 1 - The cache implements the line locking APU MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 3-29...
Page 165: Interrupt Types
• Byte ordering error from a misaligned access across a page boundary to a page with mismatched E bits • Cache locking exception • Precise external termination error and the current MSR[ME] = 1. MPC5566 Microcontroller Reference Manual, Rev. 2 3-30 Freescale Semiconductor...
Page 166 SRR[0:1] Data translation lookup did not match a valid entry in the TLB error Instruction IVOR 14 — SRR[0:1] Instruction translation lookup did not match a valid TLB entry TLB error MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 3-31...
Page 167: Bus Interface Unit (Biu)
• Timer status register (TSR)—provides status of the timer facilities. • Time base registers (TBU and TBL)—two 32-bit registers (upper and lower) that are concatenated to provide a long-period, 64-bit counter. MPC5566 Microcontroller Reference Manual, Rev. 2 3-32 Freescale Semiconductor...
Page 168: Signal Processing Extension Apu (Spe Apu)
The e200z6 core has a 64-bit architectural accumulator register that holds the results of the SPE multiply accumulate (MAC) fixed-point instructions. The accumulator allows back-to-back execution of dependent fixed-point MAC instructions, something that is found in the inner loops of DSP code such as filters. The MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 3-33...
Page 169: External References
Not the mask bit 62 of CSRR0, DSRR0, or SRR0 respectively. The destination address is [D,C]SRR0[32:62] || 0b0. bclr, bclrl, bcctr, bcctrl Not the mask bit 62 of the LR or CTR respectively. The destination address is [LR,CTR][32:62] || 0b0. MPC5566 Microcontroller Reference Manual, Rev. 2 3-34 Freescale Semiconductor...
Page 170: Introduction
All reset sources initiate execution of the MCU boot assist module (BAM) program with the exception of the software external reset. 1. Unless noted otherwise, the use of ‘clock’ or ‘clocks’ in this section is a reference to the system clock. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 171: External Signal Description
SER bit of the system reset control register (SIU_SRCR). Refer to Section 11.1.4, “FMPLL Modes of Operation” for details of PLL configuration. NOTE During a power on reset, RSTOUT is tri-stated. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 172: Reset Configuration (Rstcfg)
SIU_RSR remain set until another reset occurs. The SERF bit is set when a software external reset occurs, but no previously set bits in the SIU_RSR are cleared. Refer to Section 4.3.1.1, “Reset Status Register (SIU_RSR)” for additional information. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 173 0 No watchdog timer or debug reset occurred. 1 A watchdog timer or debug reset occurred. Checkstop reset status 0 No enabled checkstop reset occurred. 1 An enabled checkstop reset occurred. 6–13 Reserved. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 174: System Reset Control Register (Siu_Srcr)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The CRE bit is reset to 1 by POR. Other resets sources do not reset the bit value. Figure 4-2. System Reset Control Register (SIU_SRCR) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 175: Functional Description
RCHW. Hence, the available reset vector addresses are: 0x0000_0004 0x0000_4004 0x0001_0004 0x0001_C004 0x0002_0004 0x0003_0004 Serial Boot Specified over serial download MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 176: Reset Sources
RSTOUT are kept asserted until the FMPLL is locked. After the FMPLL is locked, the reset controller waits an additional predetermined number of clock cycles before negating the RSTOUT pin. The WKPCFG and BOOTCFG[0:1] pins are sampled 4 clock cycles before the negation of RSTOUT, MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 177: External Reset
SIU_RSR. The LLRS bit is set, and all other reset status bits in the SIU_RSR are cleared. Refer to Section 4.2.2, “Reset Output (RSTOUT)” Refer to Chapter 11, “Frequency Modulated Phase Locked Loop and System Clocks (FMPLL),” for more information on loss-of-lock. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 178: Loss-Of-Clock Reset
Debug tool sets the software system reset (SSR) bit in the system reset control register (SIU_SRCR) The debug tool writes a one to the software external reset (SER) bit in the system reset control register (SIU_SRCR) to generate an external software reset. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 179: Checkstop Reset
RSTCFG is asserted), and the data is updated in the SIU_RSR. The reset source status bits in the SIU_RSR are unaffected. Refer to Section 4.2.2, “Reset Output (RSTOUT).” Refer to Chapter 24, “IEEE 1149.1 Test Access Port Controller (JTAGC),” for more information. MPC5566 Microcontroller Reference Manual, Rev. 2 4-10 Freescale Semiconductor...
Page 180: Software System Reset
This reset configuration is defined by: • Configuration pins • A reset configuration halfword (RCHW), if present • Serial port, if a serial boot is used The following sections describe these configuration pins and the RCHW. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 4-11...
Page 181: Rstcfg Pin
MMU is configured, how the external bus is configured, the FlexCAN or eSCI module pin configuration, Nexus enabling, and password selection. Refer to Chapter 2, “Signal Description” for information about the BOOTCFG pins. MPC5566 Microcontroller Reference Manual, Rev. 2 4-12 Freescale Semiconductor...
Page 182: Pllcfg[0:1] Pins
0x5A. BOOT_BLOCK_ADDRESS is explained in Section 16.3.2.2.5, “Read the Reset Configuration Halfword.” The fields of the RCHW are shown in Figure 4-3. BOOT_BLOCK_ADDRESS + 0x0000_0000 Boot Identifier = 0x5A Figure 4-3. RCHW Fields MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 4-13...
Page 183 CAN/SCI boot is initiated. For an external boot, only block 0 is checked for a valid boot identifier, and if not found, a CAN/SCI boot is initiated. MPC5566 Microcontroller Reference Manual, Rev. 2 4-14 Freescale Semiconductor...
Page 184: Invalid Rchw
RCHW from the first address of each of the six blocks in the low address space (LAS) of internal flash. Table 4-9 shows the LAS addresses. Table 4-9. LAS Block Memory Addresses Block Address 0x0000_0000 0x0000_4000 0x0001_0000 0x0001_C000 0x0002_0000 0x0003_0000 MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 4-15...
Page 185: Reset Configuration Timing
4 clock cycles before the negation of RSTOUT and stored in the reset status register (SIU_RSR). BOOTCFG[0:1] are latched only if RSTCFG is asserted. WKPCFG is not dependent on RSTCFG. MPC5566 Microcontroller Reference Manual, Rev. 2 4-16 Freescale Semiconductor...
Page 186 This clock count is dependent on the configuration of the FMPLL (Refer to Section 4.2.2, “RSTOUT”). If the FMPLL is configured for 1:1 (dual controller) operation or for bypass mode, this clock count is 16000. Figure 4-4. Reset Configuration Timing MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 4-17...
Page 187: Reset Flow
False RESET asserted True Set latch, wait 8 clock cycles False RESET Set RGF bit asserted True To entry point in internal reset flow Figure 4-5. External Reset Flow Diagram MPC5566 Microcontroller Reference Manual, Rev. 2 4-18 Freescale Semiconductor...
Page 188 The clock count depends on the FMPLL configuration. Refer to Section 4.2.2, “Reset Output (RSTOUT).” If the FMPLL is configure in dual controller (1:1) or bypass mode, the clock count is 16000. Figure 4-6. Internal Reset Flow Diagram MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 4-19...
Page 189 Reset MPC5566 Microcontroller Reference Manual, Rev. 2 4-20 Freescale Semiconductor...
Page 190: Introduction
• Override the privilege level of a master to change it to user mode privilege • Designate masters as trusted or untrusted Peripherals can implement the following restrictions: MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 191 Slave 0 FLASH — Slave 1 — Slave 3 SRAM — Slave 6 PBRIDGE A PBRIDGE A FMPLL EBI control FLASH control eMIOS eTPU reg eTPU PRAM eTPU PRAM mirror eTPU SCM MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 192: Features
Supports a pair of slave accesses for 64-bit instruction fetches. • Provides configurable per-module write buffering support. • Provides configurable per-module and per-master access protections. 5.1.4 Modes of Operation The PBRIDGE has only one operating mode. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 193: External Signal Description
Additionally, these registers must only be read from or written to by a 32-bit aligned access. PBRIDGE registers are mapped into the PBRIDGE A and MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 194: Master Privilege Control Register (Pbridge_X_Mpcr)
Master trusted for writes. Determines whether the master is trusted for write accesses. Trusted by default. MTW0 0 Write accesses from the CPU are not trusted 1 Write accesses from the CPU are trusted MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 195 Master privilege level. Determines how the privilege level of the EBI is determined. Accesses not forced to MPL3 user mode by default. 0 Accesses from the EBI are forced to user mode. 1 Accesses from the EBI are not forced to user mode. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 196: Ripheral Access Control Registers (Pbridge_X_Opacr)
To ensure code compatibility across all the MPC55XX family of products, writes to those addresses must be qualified with SIU_MIDR[PARTNUM]. NOTE Write PBRIDGE_x_PACR and PBRIDGE_x_OPACR with a read/modify/write for code compatibility. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 197 The SP0 and TP0 bits default values are always used, even though the bits are writeable. The default value is 0b0000 for PACR peripheral access fields that are unused or not connected. Figure 5-3. Peripheral Access Control Registers (PBRIDGE_x_PACRn) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 198 Note: For PBRIDGE_A_PACR0 and PBRIDGE_B_PACR0, you must have supervisor privileges to access PBRIDGE registers. Note: Even though the SP0 bit (1) is writeable, the reset value for SP0 is always used. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 199 0b0101 1–7 — 0b0000 PBRIDGE_A_OPACR0 PBRIDGE_A_Base + 0x0040 FMPLL 0b0100 EBI control 0b0100 Flash control 0b0100 — 0b0100 0b0100 5–7 — 0b0100 PBRIDGE_A_OPACR1 PBRIDGE_A_Base + 0x0044 eMIOS 0b0100 1–7 — 0b0100 MPC5566 Microcontroller Reference Manual, Rev. 2 5-10 Freescale Semiconductor...
Page 200 — 0b0100 PBRIDGE_B_OPACR2 PBRIDGE_B_Base + 0x0048 FlexCAN A 0b0100 FlexCAN B 0b0100 FlexCAN C 0b0100 FlexCAN D 0b0100 4–7 — 0b0100 PBRIDGE_B_OPACR3 PBRIDGE_B_Base + 0x004C — 0b0100 1–6 — 0b0100 0b0100 MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 5-11...
Page 201: Functional Description
INTC_EOIR that consumes at least the number of system clock cycles that the actual write is delayed. Refer to Section 10.4.3.1.2, “End-of-Interrupt Exception Handler.” MPC5566 Microcontroller Reference Manual, Rev. 2 5-12 Freescale Semiconductor...
Page 202: Read Cycles
Table 5-7. On-Platform and Off-Platform Peripherals On-Platform Off-Platform Enhanced direct memory access (eDMA) Deserial serial peripheral interface (DSPI) PBridge A and B Enhanced queued analog-to-digital converter (eQADC) Interrupt controller (INTC) Enhanced serial communication interface (eSCI) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 5-13...
Page 203 The PBRIDGE also supports buffered writes, allowing write accesses to be terminated on the system bus in a single clock cycle, and then subsequently performed on the slave interface. Write buffering is controllable on a per-peripheral basis. The PBRIDGE implements a two-entry 32-bit write buffer. MPC5566 Microcontroller Reference Manual, Rev. 2 5-14 Freescale Semiconductor...
Page 204: Introduction
SIU. One signal, from the muxed signals shown on the right side of the diagram, is assigned to a ball on the device. The SIU registers are accessed using the crossbar switch. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 205 IMUX DSPI signals, and I/O channels eQADC triggers Figure 6-1. SIU Block Diagram NOTE The power-on reset detection module, pad interface/pad ring module, and peripheral I/O channels are external to the SIU. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 206: Overview
In normal mode, the SIU provides the register interface and logic that controls the device and system configuration, the reset controller, and GPIO. The SIU continues operation with no changes in stop mode. Debug SIU operation in debug mode is identical to operation in normal mode. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 207: Detailed Signal Descriptions
DDEH below the switch point value for more than two clock cycles. The switch point value is between the maximum V and minimum V specifications for the V input pins. DDEH MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 208: Reset Output (Rstout)
2. BAM module boots from internal flash (default = 0b00) 3. Boot value from internal flash is written to BOOTCFG[0:1] field in the reset status register (SIU_RSR) 4. BOOTCFG[0:1] values are latched and driven as output signals from the SIU MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 209: I/O Weak Pullup Reset Configuration (Wkpcfg)
IRQ flag bit is set to 1. For example, the IRQ flag bit is set if a rising-edge event occurs under the following conditions: • Previous filtered IRQ state was a logic 0 • Current latched IRQ state is a logic 1 • Rising-edge event is enabled for the IRQ MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 210: External Interrupts
An overrun IRQ exists for each overrun flag bit in the overrun status register (SIU_OSR). An overrun IRQ asserts when all of the following occur: • Enable bit is set in the IRQ rising- and/or falling-edge event registers (SIU_IREER, SIU_IFEER) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 211: Edge-Detect Events
SIU_MIDR MCU ID register Base + 0x0008 Reserved Base + 0x000C SIU_RSR Reset status register Base + 0x0010 SIU_SRCR System reset control register Base + 0x0014 SIU_EISR SIU external interrupt status register MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 212: Register Descriptions
The register figures use the following notational conventions in this section: Write 1 to clear the bit to 0. — Not applicable. Reserved or unimplemented bit. Bit value is uninitialized upon reset. Bit value is unchanged upon reset. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 213: Mcu Id Register (Siu_Midr)
MPC5566 reads 0x5566. CSP configuration: 0 Standard package 1 CSP package 17–19 Package settings. PKG selects the pin package for the MPC5566 device. 000 Select for Legacy compatibility 001–01x Reserved 100–101Reserved 110 Select the 416 package 110 Select the 496 calibration assembly 111 Reserved 20–23...
Page 214: Reset Status Register (Siu_Rsr)
Reset Source Priority Group • Power on reset (POR) Highest • External reset • Software system reset Higher • Loss-of-clock Lower • Loss-of-lock • Watchdog • Checkstop • Software external reset Lowest MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-11...
Page 215 0 The last reset source acknowledged by the reset controller was not a watchdog timer or debug reset. 1 The last reset source acknowledged by the reset controller was a watchdog timer or debug reset. MPC5566 Microcontroller Reference Manual, Rev. 2 6-12...
Page 216 Except for a POR request or writing a 1 to the software external reset flag (SERF) bit, all reset requests, regardless of priority are not serviced until the current reset completes. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-13...
Page 217: System Reset Control Register (Siu_Srcr)
The SSR bit always reads 0. A write of 0 to this bit has no effect. The CRE bit is set to 1 by POR. Other reset sources cannot set the CRE bit. Figure 6-4. System Reset Control Register (SIU_SRCR) MPC5566 Microcontroller Reference Manual, Rev. 2 6-14 Freescale Semiconductor...
Page 218: External Interrupt Status Register (Siu_Eisr)
The IRQ flag bit is set regardless of the state of the DMA or interrupt request enable bit in SIU_DIRER. The IRQ flag bit remains set until cleared by software or through the servicing of a DMA or interrupt request. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-15...
Page 219: Dma Interrupt Request Enable Register (Siu_Direr)
Address: Base + 0x0018 Access: R/W Reset R EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE EIRE Reset Figure 6-6. DMA Interrupt Request Enable Register (SIU_DIRER) MPC5566 Microcontroller Reference Manual, Rev. 2 6-16 Freescale Semiconductor...
Page 220: Dma/Interrupt Request Select Register (Siu_Dirsr)
DMA interrupt request select n. Selects between a DMA transfer or external interrupt request when an DIRSn edge-triggered event occurs on the corresponding IRQ[n] pin. 0 Interrupt request is selected. 1 DMA request is selected.Reserved MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-17...
Page 221: Overrun Status Register (Siu_Osr)
Overrun flag n. This bit is set when an overrun occurs on IRQ[n]. Bit 31 (OVF0) is the overrun flag for IRQ[0]; bit 16 OVFn (OVF15) is overrun flag for IRQ[15]. 0 No overrun occurred. 1 An overrun occurred. MPC5566 Microcontroller Reference Manual, Rev. 2 6-18 Freescale Semiconductor...
Page 222: Overrun Request Enable Register (Siu_Orer)
Overrun request enable n. Enables the overrun request when an overrun occurs on the IRQ[n] pin. Bit 31 (ORE0) is OREn the enable overrun flag for IRQ[0]; bit 16 (ORE15) is overrun flag for IRQ[15]. 0 Overrun request is disabled. 1 Overrun request is enabled. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-19...
Page 223: Irq Rising-Edge Event Enable Register (Siu_Ireer)
Address: Base + 0x002C Access: R/W Reset R IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE IFEE Reset Figure 6-11. IRQ Falling-Edge Event Enable Register (SIU_IFEER) MPC5566 Microcontroller Reference Manual, Rev. 2 6-20 Freescale Semiconductor...
Page 224: Irq Digital Filter Register (Siu_Idfr)
For a 100 MHz system clock, this gives a range of 20 ns to 328 µs. The minimum time of three clocks accounts for synchronization of the IRQ input pins with the system clock. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 225: Pad Configuration Registers (Siu_Pcr)
The PA fields in PCR0 through 3 and PCR4 through 7 must not be configured simultaneously to select ADDR[8:11] as an input. Only one pin is to be configured to provide the address input. Figure 6-13. Sample PCR Register Description MPC5566 Microcontroller Reference Manual, Rev. 2 6-22 Freescale Semiconductor...
Page 226 Open drain output enable. Controls output driver configuration for the pads. Either open drain or push/pull driver configurations can be selected. This feature applies to output pins only. 0 Disable open drain for the pad (push/pull driver enabled). 1 Enable open drain for the pad. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-23...
Page 227: Pad Configuration Register 0 (Siu_Pcr0)
When configured as CS[0] or ADDR[8], clear the ODE bit to 0. Refer to the EBI section for weak pullup settings when configured as CS[0] or ADDR[8]. Figure 6-14. CS[0]_ADDR[8]_GPIO[0] Pad Configuration Register (SIU_PCR0) MPC5566 Microcontroller Reference Manual, Rev. 2 6-24 Freescale Semiconductor...
Page 228: Pad Configuration Registers 1–3 (Siu_Pcr1–Siu_Pcr3)
Table 6-19 for bit field definitions. Table 6-21 lists the PA values for CS[1:3]_ADDR[9:11]_GPIO[1:3]. Table 6-21. PCR1–PCR3 PA Field Descriptions PA Field Pin Function 0b00 GPIO[1:3] 0b01 CS[1:3] 0b10 ADDR[9:11] 0b11 CS[1:3] MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-25...
Page 229: Pad Configuration Registers 4–7 (Siu_Pcr4–Siu_Pcr7)
If external master operation is enabled, clear the HYS bit to 0. Refer to the EBI section for weak pullup settings when configured as ADDR[8:26]. Figure 6-17. ADDR[12:26]_GPIO[8:22] Pad Configuration Registers (SIU_PCR8–SIU_PCR22) MPC5566 Microcontroller Reference Manual, Rev. 2 6-26 Freescale Semiconductor...
Page 230: Pad Configuration Registers 23–25 (Siu_Pcr23–Siu_Pcr25)
Figure 6-18. ADDR[27:29]_GPIO[23:25] Pad Configuration Registers (SIU_PCR23–SIU_PCR25) Refer to Table 6-19 for bit field definitions. Table 6-24 lists the PA field for ADDR[27:29]_GPIO[23:25]. Table 6-24. PCR23–PCR25 PA Field Descriptions PA Field Pin Function GPIO[23:25] ADDR[27:29] MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-27...
Page 231: Pad Configuration Registers 26–27 (Siu_Pcr26–Siu_Pcr27)
If external master operation is enabled, clear the HYS bit to 0. Refer to the EBI section for weak pullup settings when configured as DATA[0:15]. Figure 6-20. DATA[0:15]_GPIO[28:43] Pad Configuration Registers (SIU_PCR28–SIU_PCR43) MPC5566 Microcontroller Reference Manual, Rev. 2 6-28 Freescale Semiconductor...
Page 232: Pad Configuration Registers 44 (Siu_Pcr44)
Refer to the EBI section for weak pullup settings when configured as DATA[17]. Figure 6-22. DATA[17]_FEC_CRS_GPIO[45] Pad Configuration Registers (SIU_PCR45) 6.3.1.22 Pad Configuration Registers 46 (SIU_PCR46) The SIU_PCR46 register controls the function, direction, and electrical attributes of DATA[18]_FEC_TX_ER_GPIO[46]. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-29...
Page 233: Pad Configuration Registers 47 (Siu_Pcr47)
If external master operation is enabled, clear the HYS bit to 0. Refer to the EBI section for weak pullup settings when configured as DATA[20]. Figure 6-25. DATA[20]_FEC_TXD[0]_GPIO[48] Pad Configuration Registers (SIU_PCR48) MPC5566 Microcontroller Reference Manual, Rev. 2 6-30 Freescale Semiconductor...
Page 234: Pad Configuration Registers 49 (Siu_Pcr49)
If external master operation is enabled, clear the HYS bit to 0. Refer to the EBI section for weak pullup settings when configured as DATA[22] FEC_RXD[0]. Figure 6-27. DATA[22]_FEC_RXD[0] GPIO[50] Pad Configuration Registers (SIU_PCR50) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-31...
Page 235: Pad Configuration Registers 51 (Siu_Pcr51)
Table 6-19 for bit field definitions. Table 6-28 lists the PA fields for DATA[23]_FEC_TXD[3]_GPIO[51]. Table 6-28. PCR51 PA Field Descriptions PA Field Pin Function 0b00 GPIO[51] 0b01 DATA[23] 0b10 FEC_TXD[3] 0b11 DATA[23] MPC5566 Microcontroller Reference Manual, Rev. 2 6-32 Freescale Semiconductor...
Page 236: Pad Configuration Registers 52 (Siu_Pcr52)
If external master operation is enabled, clear the HYS bit to 0. Refer to the EBI section for weak pullup settings when configured as DATA[25] or FEC_RX_DV. Figure 6-30. DATA[25]_FEC_RX_DV_GPIO[53] Pad Configuration Registers (SIU_PCR53) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-33...
Page 237: Pad Configuration Registers 54 (Siu_Pcr54)
Table 6-19 for bit field definitions. Table 6-31 lists the PA fields for DATA[26]_FEC_TX_EN_GPIO[54]. Table 6-31. PCR54 PA Field Descriptions PA Field Pin Function 0b00 GPIO[54] 0b01 DATA[26] 0b10 FEC_RX_DV 0b11 DATA[26] MPC5566 Microcontroller Reference Manual, Rev. 2 6-34 Freescale Semiconductor...
Page 238: Pad Configuration Registers 55 (Siu_Pcr55)
If external master operation is enabled, clear the HYS bit to 0. Refer to the EBI section for weak pullup settings when configured as DATA[28] or FEC_TXD[1]. Figure 6-33. DATA[28]_FEC_TXD[1]_GPIO[56] Pad Configuration Registers (SIU_PCR56) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-35...
Page 239: Pad Configuration Registers 57 (Siu_Pcr57)
Table 6-19 for bit field definitions. Table 6-34 lists the PA fields for DATA[29]_FEC_RXD[1]_GPIO[57]. Table 6-34. PCR57 PA Field Descriptions PA Field Pin Function 0b00 GPIO[57] 0b01 DATA[29] 0b10 FEC_RXD[1] 0b11 DATA[29] MPC5566 Microcontroller Reference Manual, Rev. 2 6-36 Freescale Semiconductor...
Page 240: Pad Configuration Registers 58 (Siu_Pcr58)
If external master operation is enabled, clear the HYS bit to 0. Refer to the EBI section for weak pullup settings when configured as DATA[31] or FEC_RXD[3]. Figure 6-36. DATA[31]_FEC_RXD[3]_GPIO[59] Pad Configuration Registers (SIU_PCR59) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-37...
Page 241: Pad Configuration Registers 60–61 (Siu_Pcr60–Siu_Pcr61)
Figure 6-37. TSIZ[0:1]_GPIO[60:61] Pad Configuration Register (SIU_PCR60–SIU_PCR61) Refer to Table 6-19 for bit field definitions. Table 6-46 lists the PA fields for TSIZ[0:1]_GPIO[60:61]. Table 6-37. PCR60–PCR61 PA Field Definition PA Field Pin Function GPIO[60:61] TSIZ[0:1] MPC5566 Microcontroller Reference Manual, Rev. 2 6-38 Freescale Semiconductor...
Page 242: Pad Configuration Register 62 (Siu_Pcr62)
Figure 6-39. BDIP_GPIO[63] Pad Configuration Register (SIU_PCR63) Refer to Table 6-19 for bit field definitions. Table 6-46 lists the PA fields for BDIP_GPIO[63]. Table 6-39. PCR63 PA Field Definition PA Field Pin Function GPIO[63] BDIP MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-39...
Page 243: Pad Configuration Registers 64–65 (Siu_Pcr64–Siu_Pcr65)
Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. When configured as WE/BE[2:3], clear the ODE bit to 0. Refer to the EBI section for weak pullup settings when configured as WE/BE[2:3]. Figure 6-41. WE/BE[2:3]_GPIO[66:67] Pad Configuration Registers (SIU_PCR66–SIU_PCR67) MPC5566 Microcontroller Reference Manual, Rev. 2 6-40 Freescale Semiconductor...
Page 244: Pad Configuration Register 68 (Siu_Pcr68)
When configured as TS, clear the ODE bit to 0. When EBI is enabled, clear the HYS bit to 0. Refer to the EBI section for weak pullup settings when configured as TS. Figure 6-43. TS_GPIO[69] Pad Configuration Register (SIU_PCR69) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-41...
Page 245: Pad Configuration Register 70 (Siu_Pcr70)
PA fields for TA_GPIO[70]. Table 6-44. PCR70 PA Field Definition PA Field Pin Function GPIO[70] 6.3.1.44 Pad Configuration Register 71 (SIU_PCR71) The SIU_PCR71 register controls the function, direction, and electrical attributes of TEA_GPIO[71]. MPC5566 Microcontroller Reference Manual, Rev. 2 6-42 Freescale Semiconductor...
Page 246: Pad Configuration Register 72 (Siu_Pcr72)
Table 6-19 for bit field definitions. Table 6-46 lists the PA field for BR_FEC_MDC_GPIO[72]. Table 6-46. PCR72 PA Field Definition PA Field Pin Function 0b00 GPIO[72] 0b01 0b10 FEC_MDC 0b11 Invalid value MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-43...
Page 247: Pad Configuration Register 73 (Siu_Pcr73)
If external master operation is enabled, clear the HYS bit to 0. Refer to the EBI section for weak pullup settings when configured as BB. Figure 6-48. BB_GPIO[74] Pad Configuration Register PCR74 MPC5566 Microcontroller Reference Manual, Rev. 2 6-44 Freescale Semiconductor...
Page 248: Pad Configuration Register 82–75 (Siu_Pcr82–Siu_Pcr75)
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. Figure 6-50. CNTXA_TXDA_GPIO[83] Pad Configuration Register (SIU_PCR83) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-45...
Page 249: Pad Configuration Register 84 (Siu_Pcr84)
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. Figure 6-52. CNTXB_PCSC[3]_GPIO[85] Pad Configuration Register (SIU_PCR85) MPC5566 Microcontroller Reference Manual, Rev. 2 6-46 Freescale Semiconductor...
Page 250: Pad Configuration Register 86 (Siu_Pcr86)
Table 6-19 for bit field definitions. Table 6-52 lists the PA fields for CNRXB_PCSC[4]_GPIO[86]. Table 6-52. PCR86 PA Field Definitions PA Field Pin Function 0b00 GPIO[86] 0b01 CNRXB 0b10 PCSC[4] 0b11 CNRXB MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-47...
Page 251: Pad Configuration Register 87 (Siu_Pcr87)
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. Figure 6-55. CNRXC_PCSD[4]_GPIO[88] Pad Configuration Register (SIU_PCR88) MPC5566 Microcontroller Reference Manual, Rev. 2 6-48 Freescale Semiconductor...
Page 252: Pad Configuration Register 89 (Siu_Pcr89)
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. Figure 6-57. RXDA_GPIO[90] Pad Configuration Register (SIU_PCR90) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-49...
Page 253: Pad Configuration Register 91 (Siu_Pcr91)
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. Figure 6-59. RXDB_PCSD[5]_GPIO[92] Pad Configuration Register (SIU_PCR92) MPC5566 Microcontroller Reference Manual, Rev. 2 6-50 Freescale Semiconductor...
Page 254: Pad Configuration Register 93 (Siu_Pcr93)
WPE WPS RESET: The SCKA function is available on the MPC5566 only. When SCKA is configured for master operation, set the OBE bit to 1, or clear to 0 for slave operation. When configured as GPDO, set the OBE bit to 1.
Page 255: Pad Configuration Register 94 (Siu_Pcr94)
WPE WPS RESET: The SINA function is available on the MPC5566 only. When configured as SINA or PCSC[2], the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1. When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register.
Page 256: Pad Configuration Registers 96 (Siu_Pcr96)
WPE WPS RESET: The PCSA[0] function is available on the MPC5566 only. When configured as PSCA[0], set the OBE bit to 1 for master operation, and clear to 0 for slave operation. When configures as PCSD[2], the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1.
Page 257: Pad Configuration Registers 97 (Siu_Pcr97)
WPE WPS RESET: The PCSA[1] function is available on the MPC5566 only. When configured as PCSA[1] or PCSB[2], the OBE bit has no effect. When configured as GPDO, set the OBE bit to 1. When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register.
Page 258: Pad Configuration Register 99 (Siu_Pcr99)
Table 6-19 for bit field definitions. Table 6-65 lists the PA fields for PCSA[3]_SIND_GPIO[99]. Table 6-65. PCR99 PA Field Definitions PA Field Pin Function 0b00 GPIO[99] 0b01 PCSA[3] 0b10 SIND 0b11 PCSA[3] MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-55...
Page 259: Pad Configuration Register 100 (Siu_Pcr100)
WPE WPS RESET: The PCSA[4] function is available on the MPC5566 only. When configured as PCSA[4] or SOUTD, the OBE bit has no effect. When configured as GPDO, set the OBE to 1. When PCSA[4] or SOUTD is configured for slave operation, set the IBE bit to 1. When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register.
Page 260: Pad Configuration Register 102 (Siu_Pcr102)
Table 6-19 for bit field definitions. Table 6-68 lists the PA fields for SCKB_PCSC[1]_GPIO[102]. Table 6-68. PCR102 PA Field Definitions PA Field Pin Function 0b00 GPIO[102] 0b01 SCKB 0b10 PCSC[1] 0b11 SCKB MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-57...
Page 261: Pad Configuration Register 103 (Siu_Pcr103)
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. Figure 6-71. SOUTB_PCSC[5]_GPIO[104] Pad Configuration Register (SIU_PCR104) MPC5566 Microcontroller Reference Manual, Rev. 2 6-58 Freescale Semiconductor...
Page 262: Pad Configuration Register 105 (Siu_Pcr105)
Table 6-19 for bit field definitions. Table 6-71 lists the PA fields for PCSB[0]_PCSD[2]_GPIO[105]. Table 6-71. PCR105 PA Field Definitions PA Field Pin Function 0b00 GPIO[105] 0b01 PCSB[0] 0b10 PCSD[2] 0b11 PCSB[0] MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-59...
Page 263: Pad Configuration Register 106 (Siu_Pcr106)
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. Figure 6-74. PCSB[2]_SOUTC_GPIO[107] Pad Configuration Register (SIU_PCR107) MPC5566 Microcontroller Reference Manual, Rev. 2 6-60 Freescale Semiconductor...
Page 264: Pad Configuration Register 108 (Siu_Pcr108)
Table 6-19 for bit field definitions. Table 6-74 lists the PA fields for PCSB[3]_SINC_GPIO[108]. Table 6-74. PCR108 PA Field Definitions PA Field Pin Function 0b00 GPIO[108] 0b01 PCSB[3] 0b10 SINC 0b11 PCSB[3] MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-61...
Page 265: Pad Configuration Register 109 (Siu_Pcr109)
1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. Figure 6-77. PCSB[5]_PCSC[0]_GPIO[110] Pad Configuration Register (SIU_PCR110) MPC5566 Microcontroller Reference Manual, Rev. 2 6-62 Freescale Semiconductor...
Page 266: Pad Configuration Registers 111–112 (Siu_Pcr111–Siu_Pcr112)
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1. Figure 6-79. TCRCLKA_IRQ[7]_GPIO[113] Pad Configuration Register (SIU_PCR113) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-63...
Page 267: Pad Configuration Register 114–117 (Siu_Pcr114–Siu_Pcr117)
Table 6-19 for bit field definitions. Table 6-79 lists the PA fields for ETPUA[0:3]_ETPUA[12:15]_GPIO[114:117]. Table 6-79. PCR114–PCR117 PA Field Definitions PA Field Pin Function 0b00 GPIO[114:117] 0b01 ETPUA[0:3] 0b10 ETPUA[12:15] 0b11 ETPUA[0:3] MPC5566 Microcontroller Reference Manual, Rev. 2 6-64 Freescale Semiconductor...
Page 268: Pad Configuration Register 118 (Siu_Pcr118)
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. The weak pullup/down value at reset for ETPUA[5] and ETPUA[17], is determined by WKPCFG. Figure 6-82. ETPUA[5]_ETPUA[17]_GPIO[119] Pad Configuration Register (SIU_PCR119) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-65...
Page 269: Pad Configuration Register 120 (Siu_Pcr120)
Table 6-19 for bit field definitions. Table 6-82 lists the PA fields for ETPUA[6]_ETPUA[18]_GPIO[120]. Table 6-82. PCR120 PA Field Definitions PA Field Pin Function 0b00 GPIO[120] 0b01 ETPUA[6] 0b10 ETPUA[18] 0b11 ETPUA[6] MPC5566 Microcontroller Reference Manual, Rev. 2 6-66 Freescale Semiconductor...
Page 270: Pad Configuration Register 121 (Siu_Pcr121)
Table 6-19 for bit field definitions. Table 6-83 lists the PA fields for ETPUA[7]_ETPUA[19]_GPIO[121]. Table 6-83. PCR121 PA Field Definitions PA Field Pin Function 0b00 GPIO[121] 0b01 ETPUA[7] 0b10 ETPUA[19] 0b11 ETPUA[7] MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-67...
Page 271: Pad Configuration Registers 122–124 (Siu_Pcr122–Siu_Pcr124)
IBE bit to 1 allows the pin state to be reflected in the corresponding GPDI register. The weak pullup/down selection at reset for the ETPUA[11] pin is determined by the WKPCFG pin. Figure 6-86. ETPUA[11]_ETPUA[23]_GPIO[125] Pad Configuration Register (SIU_PCR125) MPC5566 Microcontroller Reference Manual, Rev. 2 6-68 Freescale Semiconductor...
Page 272: Pad Configuration Register 126 (Siu_Pcr126)
Table 6-19 for bit field definitions. Table 6-86 lists the PA fields for ETPUA[12]_PCSB[1]_GPIO[126]. Table 6-86. PCR126 PA Field Definitions PA Field Pin Function 0b00 GPIO[126] 0b01 ETPUA[12] 0b10 PCSB[1] 0b11 ETPUA[12] MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-69...
Page 273: Pad Configuration Registers 127–129 (Siu_Pcr127–Siu_Pcr129)
IBE bit to 1 to show the pin state in the GPDI register. The weak pullup/down selection at reset for the ETPUA[16:19] pin is determined by the WKPCFG pin. Figure 6-89. ETPUA[16:19]_PCSD[1:4]_GPIO[130:133] Pad Configuration Register (SIU_PCR130–SIU_PCR133) MPC5566 Microcontroller Reference Manual, Rev. 2 6-70 Freescale Semiconductor...
Page 274: Pad Configuration Register 134 (Siu_Pcr134)
Table 6-19 for bit field definitions. Table 6-89 lists the PA fields for ETPUA[20]_IRQ[8]_GPIO[134]. Table 6-89. PCR134 PA Field Definitions PA Field Pin Function 0b00 GPIO[134] 0b01 ETPUA[20] 0b10 IRQ[8] 0b11 ETPUA[20] MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-71...
Page 275: Pad Configuration Register 135 (Siu_Pcr135)
Clear the IBE bit to 0 to reduce power consumption. The IBE bit must be set to 1 for ETPUA[22] or GPIO[136] when configured as input. The weak pullup/down selection at reset for the ETPUA[22] pin is determined by the WKPCFG pin. Figure 6-92. ETPUA[22]_IRQ[10]_GPIO[136] Pad Configuration Register (SIU_PCR136) MPC5566 Microcontroller Reference Manual, Rev. 2 6-72 Freescale Semiconductor...
Page 276: Pad Configuration Register 137 (Siu_Pcr137)
Table 6-19 for bit field definitions. Table 6-92 lists the PA fields for ETPUA[23]_IRQ[11]_GPIO[137]. Table 6-92. PCR137 PA Field Definitions PA Field Pin Function 0b00 GPIO[137] 0b01 ETPUA[23] 0b10 IRQ[11] 0b11 ETPUA[23] MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-73...
Page 277: Pad Configuration Registers 138–141 (Siu_Pcr138–Siu_Pcr141)
IBE bit to 0 to reduce power consumption. The IBE bit must be set to 1 for GPIO when configured as input. The weak pullup/down value at reset for ETPUA[28:30] is determined by WKPCFG. Figure 6-95. ETPUA[28:30]_PCSC[1:3]_GPIO[142:144] Pad Configuration Register (SIU_PCR142–SIU_PCR144) MPC5566 Microcontroller Reference Manual, Rev. 2 6-74 Freescale Semiconductor...
Page 278: Pad Configuration Register 145 (Siu_Pcr145)
Table 6-95. PCR145 PA Field Definitions PA Field Pin Function 0b00 GPIO[145] 0b01 ETPUA[31] 0b10 PCSC[4] 0b11 ETPUA[31] 6.3.1.96 Pad Configuration Register 146 (SIU_PCR146) The SIU_PCR146 register controls the function, direction, and electrical attributes of TCRCLKB_IRQ[6]_GPIO[146]. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-75...
Page 279: Pad Configuration Registers 147–162 (Siu_Pcr147–Siu_Pcr162)
The IBE bit must be set to 1 for ETPUB[0:15] or GPIO[147:162] when configured as inputs. The weak pullup/down selection at reset for the ETPUB[0:15] pins is determined by the WKPCFG pin. Figure 6-98. ETPUB[0:15]_ETPUB[16:31]_GPIO[147:162] Pad Configuration Registers (SIU_PCR147–SIU_PCR162) MPC5566 Microcontroller Reference Manual, Rev. 2 6-76 Freescale Semiconductor...
Page 280: Pad Configuration Registers 163 (Siu_Pcr163–Siu_Pcr166)
Table 6-19 for bit field definitions. Table 6-98 lists the PA fields for ETPUB[16:19]_PCSA[1:4]_GPIO[163:166]. Table 6-98. PCR163–PCR164 PA Field Definitions PA Field Pin Function 0b00 GPIO[163:166] 0b01 ETPUB[16:19] 0b10 PCSA[1:4] 0b11 ETPUB[16:19] MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-77...
Page 281: Pad Configuration Registers 167–178 (Siu_Pcr167–Siu_Pcr178)
The IBE bit must be set to 1 for EMIOS[0:9] or GPIO[179:188] when configured as inputs. The weak pullup/down selection at reset for the EMIOS[0:9] pins is determined by the WKPCFG pin. Figure 6-101. EMIOS[0:9]_ETPUA[0:9]_GPIO[179:188] Pad Configuration Register (SIU_PCR179–SIU_PCR188) MPC5566 Microcontroller Reference Manual, Rev. 2 6-78 Freescale Semiconductor...
Page 282: Pad Configuration Register 189–190 (Siu_Pcr189–Siu_Pcr190)
Figure 6-102. EMIOS[10:11]_PCSD[3:4]_GPIO[189:190] Pad Configuration Register (SIU_PCR189–SIU_PCR190) Refer to Table 6-19 for bit field definitions. Table 6-101 lists the PA fields for EMIOS[10:11]_PCSD[3:4]_GPIO[189:190]. Table 6-101. PCR189–PCR190 PA Field Definitions Pin Function GPIO[189:190] EMIOS[10:11] PCSD[3:4] EMIOS[10:11] MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-79...
Page 283: Pad Configuration Register 191 (Siu_Pcr191)
The IBE bit must be set to 1 for GPIO[192] when configured as an input. The weak pullup/down selection at reset for the EMIOS[13] pin is determined by the WKPCFG pin. Figure 6-104. EMIOS[13]_SOUTD_GPIO[192] Pad Configuration Register (SIU_PCR192) MPC5566 Microcontroller Reference Manual, Rev. 2 6-80 Freescale Semiconductor...
Page 284: Pad Configuration Register 193 (Siu_Pcr193)
Table 6-104 lists the PA fields for EMIOS[14]_IRQ[0]_CNTXD_GPIO[193]. Table 6-104. PCR193 PA Field Definitions PA Field Pin Function 0b000 GPIO[193] 0b001 EMIOS[14] 0b010 IRQ[0] 0b011 EMIOS[14] 0b100 CNTXD MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-81...
Page 285: Pad Configuration Register 194 (Siu_Pcr194)
The IBE bit must be set to 1 for EMIOS[16] or GPIO[195] when configured as input. The weak pullup/down selection at reset for the EMIOS[16] pin is determined by the WKPCFG pin. Figure 6-107. EMIOS[16]_ETPUB[0]_GPIO[195] Pad Configuration Register (SIU_PCR195) MPC5566 Microcontroller Reference Manual, Rev. 2 6-82 Freescale Semiconductor...
Page 286: Pad Configuration Register 196 (Siu_Pcr196)
Table 6-19 for bit field definitions. Table 6-107 lists the PA fields for EMIOS[17]_ETPUB[1]_GPIO[196]. Table 6-107. PCR196 PA Field Definitions PA Field Pin Function 0b00 GPIO[196] 0b01 EMIOS[17] 0b10 ETPUB[1] 0b11 EMIOS[17] MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-83...
Page 287: Pad Configuration Register 197 (Siu_Pcr197)
The IBE bit must be set to 1 for EMIOS[19] or GPIO[198] when configured as input. The weak pullup/down selection at reset for the EMIOS[19] pins is determined by the WKPCFG pin. Figure 6-110. EMIOS[19]_ETPUB[3]_GPIO[198] Pad Configuration Register (SIU_PCR198) MPC5566 Microcontroller Reference Manual, Rev. 2 6-84 Freescale Semiconductor...
Page 288: Pad Configuration Registers 199–200 (Siu_Pcr199–Siu_Pcr200)
Table 6-19 for bit field definitions. Table 6-110 lists the PA fields for EMIOS[20:21]_ETPUB[4:5]_GPIO[199:200]. Table 6-110. PCR199–PCR200 PA Field Definitions PA Field Pin Function 0b00 GPIO[199:200] 0b01 EMIOS[20:21] 0b10 ETPUB[4:5] 0b11 EMIOS[20:21] MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-85...
Page 289: Pad Configuration Register 201 (Siu_Pcr201)
The IBE bit must be set to 1 for EMIOS[23] or GPIO[202] when configured as input. The weak pullup/down selection at reset for the EMIOS[23] pin is determined by the WKPCFG pin. Figure 6-113. EMIOS[23]_ETPUB[7]_GPIO[202] Pad Configuration Register (SIU_PCR202) MPC5566 Microcontroller Reference Manual, Rev. 2 6-86 Freescale Semiconductor...
Page 290: Pad Configuration Registers 203–204 (Siu_Pcr203–Siu_Pcr204)
The SIU_PCR205 register controls the direction and electrical attributes of the GPIO[205] pin. This register is separate from the PCRs for GPIO[206:207] since GPIO[205] is a medium pad type with slew MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-87...
Page 291: Pad Configuration Registers 206–207 (Siu_Pcr206–Siu_Pcr207)
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. When configured as GPDI, set the IBE bit to 1. Figure 6-116. GPIO[206:207] Pad Configuration Registers (SIU_PCR206–SIU_PCR207) MPC5566 Microcontroller Reference Manual, Rev. 2 6-88 Freescale Semiconductor...
Page 292: Pad Configuration Register 208 (Siu_Pcr208)
When configured as GPDI, set the IBE bit to 1. When configured as IRQ[5], set the HYS bit to 1. Figure 6-118. PLLCFG[1]_IRQ[5]_SOUTD_GPIO[209] Pad Configuration Register (SIU_PCR209) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-89...
Page 293: Pad Configuration Register 210 (Siu_Pcr210)
Figure 6-119. RSTCFG_GPIO[210] Pad Configuration Register (SIU_PCR210) Refer to Table 6-19 for bit field definitions. Table 6-116 lists the PA fields for RSTCFG_GPIO[210]. Table 6-116. PCR210 PA Field Definitions PA Field Pin Function GPIO RSTCFG MPC5566 Microcontroller Reference Manual, Rev. 2 6-90 Freescale Semiconductor...
Page 294: Pad Configuration Registers 211–212 (Siu_Pcr211–Siu_Pcr212)
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the corresponding GPDI register. When configured as GPDI, set the IBE bit to 1. Figure 6-121. WKPCFG_GPIO[213] Pad Configuration Register (SIU_PCR213) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-91...
Page 295: Pad Configuration Register 214 (Siu_Pcr214)
Table 6-19 for bit field definitions. Table 6-119 lists the PA fields for AN[12]_MA[0]_SDS. Table 6-119. PCR215 PA Field Definitions PA Field Pin Function 0b00 0b01 Invalid value 0b10 MA[0] 0b11 AN[12] MPC5566 Microcontroller Reference Manual, Rev. 2 6-92 Freescale Semiconductor...
Page 296: Pad Configuration Register 216 (Siu_Pcr216)
Table 6-19 for bit field definitions. Table 6-121 lists the PA fields for AN[14]_MA[2]_SDI. Table 6-121. PCR217 PA Field Definitions PA Field Pin Function 0b00 0b01 Invalid value 0b10 MA[2] 0b11 AN[14] MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-93...
Page 297: Pad Configuration Register 218 (Siu_Pcr218)
Figure 6-127. MCKO Pad Configuration Register (SIU_PCR219) 6.3.1.127 Pad Configuration Register 223–220 (SIU_PCR223–SIU_PCR220) The SIU_PCR223–SIU_PCR220 registers control the drive strength of MDO[3:0]. Address: Base + (0x01FE–0x01F8) Access: R/W RESET: Figure 6-128. MDO[3:0 ] Pad Configuration Register (SIU_PCR223–SIU_PCR220) MPC5566 Microcontroller Reference Manual, Rev. 2 6-94 Freescale Semiconductor...
Page 298: Pad Configuration Register 225–224 (Siu_Pcr225–Siu_Pcr224)
Figure 6-131. EVTO Pad Configuration Register (SIU_PCR227) 6.3.1.131 Pad Configuration Register 228 (SIU_PCR228) The SIU_PCR228 register controls the drive strength of TDO. Address: Base + 0x0208 Access: R/W RESET: Figure 6-132. TDO Pad Configuration Register (SIU_PCR228) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-95...
Page 299: Pad Configuration Register 229 (Siu_Pcr229)
Figure 6-135. CAL_CS[0] Pad Configuration Register (SIU_PCR256) Refer to Table 6-19 for bit field definitions. Table 6-123 lists the PA fields for CAL_CS[0]. Table 6-123. PCR256 PA Field Definition PA Field Pin Function Invalid value CAL_CS[0] MPC5566 Microcontroller Reference Manual, Rev. 2 6-96 Freescale Semiconductor...
Page 300: Pad Configuration Registers 257–258 (Siu_Pcr257–Siu_Pcr258)
6.3.1.138 Pad Configuration Register 260 (SIU_PCR260) The SIU_PCR260 register controls the function, direction, and electrical attributes of CAL_ADDR[13]. Address: Base + 0x0248 Access: R/W RESET: Figure 6-138. CAL_ADDR[13] Pad Configuration Register (SIU_PCR260) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-97...
Page 301: Pad Configuration Register 261 (Siu_Pcr261)
Figure 6-139. CAL_ADDR[14] Pad Configuration Register (SIU_PCR261) Refer to Table 6-19 for bit field definitions. Table 6-127 lists the PA fields for CAL_ADDR[14]. Table 6-127. PCR261 PA Field Definitions PA Field Pin Function Invalid value CAL_ADDR[14] MPC5566 Microcontroller Reference Manual, Rev. 2 6-98 Freescale Semiconductor...
Page 302: Pad Configuration Register 262 (Siu_Pcr262)
6.3.1.142 Pad Configuration Register 264 (SIU_PCR264) The SIU_PCR264 register controls the function, direction, and electrical attributes of CAL_ADDR[17]. Address: Base + 0x0250 Access: R/W RESET: Figure 6-142. CAL_ADDR[17] Pad Configuration Register (SIU_PCR264) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-99...
Page 303: Pad Configuration Register 265 (Siu_Pcr265)
Figure 6-144. CAL_ADDR[19] Pad Configuration Register (SIU_PCR266) Refer to Table 6-19 for bit field definitions. Table 6-132 lists the PA fields for CAL_ADDR[19]. Table 6-132. PCR266 PA Field Definitions PA Field Pin Function Invalid value CAL_ADDR[19] MPC5566 Microcontroller Reference Manual, Rev. 2 6-100 Freescale Semiconductor...
Page 304: Pad Configuration Register 267 (Siu_Pcr267)
6.3.1.147 Pad Configuration Register 269 (SIU_PCR269) The SIU_PCR269 register controls the function, direction, and electrical attributes of CAL_ADDR[22]. Address: Base + 0x025A Access: R/W RESET: Figure 6-147. CAL_ADDR[22] Pad Configuration Register (SIU_PCR269) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-101...
Page 305: Pad Configuration Registers 270–271 (Siu_Pcr270–Siu_Pcr271)
Pad Configuration Registers (SIU_PCR272–SIU_PCR274) Refer to Table 6-19 for bit field definitions. Table 6-137 lists the PA fields for CAL_ADDR[25:27]. Table 6-137. PCR272–PCR274 PA Field Definitions PA Field Pin Function Invalid value CAL_ADDR[25:27] MPC5566 Microcontroller Reference Manual, Rev. 2 6-102 Freescale Semiconductor...
Page 306: Pad Configuration Register 275 (Siu_Pcr275)
6.3.1.152 Pad Configuration Register 277 (SIU_PCR277) The SIU_PCR277 register controls the function, direction, and electrical attributes of CAL_ADDR[30]. Address: Base + 0x026A Access: R/W RESET: Figure 6-152. CAL_ADDR[30] Pad Configuration Registers (SIU_PCR277) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-103...
Page 307: Pad Configuration Register 278–293 (Siu_Pcr278–Siu_Pcr293)
Figure 6-154. CAL_RD_WR Pad Configuration Registers (SIU_PCR294) Refer to Table 6-19 for bit field definitions. Table 6-142 lists the PA fields for CAL_RD_WR. Table 6-142. PCR294 PA Field Definition PA Field Pin Function Invalid value CAL_RD_WR MPC5566 Microcontroller Reference Manual, Rev. 2 6-104 Freescale Semiconductor...
Page 308: Pad Configuration Register 295–296 (Siu_Pcr295–Siu_Pcr296)
6.3.1.157 Pad Configuration Register 298 (SIU_PCR298) The SIU_PCR298 register controls the function, direction, and electrical attributes of CAL_TS. Address: Base + 0x0294 Access: R/W RESET: Figure 6-157. CAL_TS Pad Configuration Registers (SIU_PCR298) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-105...
Page 309: Pad Configuration Register 299 (Siu_Pcr299)
If the direction of a GPIO signal changes from input to output, the SIU_GPDOn register value is automatically driven out to the external pin without a software update. MPC5566 Microcontroller Reference Manual, Rev. 2 6-106 Freescale Semiconductor...
Page 310: Gpio Pin Data Input Registers 0–213 (Siu_Gpdin)
PCR register, the SIU_GPDIn register reflects the state of the output pin. Address: SIU_BASE + 0x0800 PDIn Reset Figure 6-160. General Purpose Data Input (GPDI) Registers 0–213 (SIU_GPDIn) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-107...
Page 311: Eqadc Trigger Input Select Register (Siu_Etisr)
CFIFO Channel Channel Channel Input GPIO[207] Number) eTPUA[30] eMIOS[10] ETRIG[0] GPIO[206] eTPUA[31] eMIOS[11] ETRIG[1] GPIO[207] eTPUA[29] eMIOS[15] ETRIG[0] GPIO[206] eTPUA[28] eMIOS[14] ETRIG[1] GPIO[207] eTPUA[27] eMIOS[13] ETRIG[0] GPIO[206] eTPUA[26] eMIOS[12] ETRIG[1] GPIO[207] MPC5566 Microcontroller Reference Manual, Rev. 2 6-108 Freescale Semiconductor...
Page 312 10 EMIOS[15] channel 11 ETRIG[0] pin 8–9 TSEL1 eQADC trigger input select 1. Specifies the input for eQADC trigger 1. [0:1] 00 GPIO[207] 01 ETPUA[31] channel 10 EMIOS[11] channel 11 ETRIG[1] pin MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-109...
Page 313: External Irq Input Select Register (Siu_Eiisr)
11 PCSD[0] serialized input (ETPUA[21]) 4–5 ESEL13 External IRQ input select 13. Specifies the input for IRQ[13]. [0:1] 00 IRQ[13] 01 PCSB[13] serialized input (ETPUA[24]) 10 PCSC[14] serialized input (ETPUA[10]) 11 PCSD[15] serialized input (ETPUA[24]) MPC5566 Microcontroller Reference Manual, Rev. 2 6-110 Freescale Semiconductor...
Page 314 11 PCSD[7] serialized input (EMIOS[10]) 22–23 ESEL4 External IRQ input select 4. Specifies the input for IRQ[4]. [0:1] 00 IRQ[4] 01 PCSB[4] serialized input (ETPUA[19]) 10 PCSC[5] serialized input (ETPUA[1]) 11 PCSD[6] serialized input (EMIOS[11]) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-111...
Page 315: Dspi Input Select Register (Siu_Disr)
Address: Base + 0x0908 Access: R/W SINSELA SSSELA SCKSELA TRIGSELA SINSELB SSSELB SCKSELB TRIGSELB Reset SINSELC SSSELC SCKSELC TRIGSELC SINSELD SSSELD SCKSELD TRIGSELD Reset Figure 6-163. DSPI Input Select Register (SIU_DISR) MPC5566 Microcontroller Reference Manual, Rev. 2 6-112 Freescale Semiconductor...
Page 316 14–15 TRIGSELB DSPI B trigger input select. Specifies the source of the DSPI B trigger input for [0:1] master or slave mode. 00 Invalid value 01 PCSA[4] 10 PCSC[4] 11 PCSD[4] MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-113...
Page 317 30–31 TRIGSELD DSPI D trigger input select. Specifies the source of the DSPI D trigger input for [0:1] master or slave mode. 00 Invalid value 01 PCSA4 10 PCSB4 11 PCSC4 MPC5566 Microcontroller Reference Manual, Rev. 2 6-114 Freescale Semiconductor...
Page 318: Chip Configuration Register (Siu_Ccr)
0 Nexus disable input signal is negated. 1 Nexus disable input signal is asserted. 16–29 — Reserved MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-115...
Page 319: External Clock Control Register (Siu_Eccr)
ENGCLK and CLKOUT. All bits and fields in the SIU_ECCR are read/write and are reset by the synchronous reset signal. Address: Base + 0x0984 Access: R/W Reset ENGDIV EBTS EBDF Reset Figure 6-165. External Clock Control Register (SIU_ECCR) MPC5566 Microcontroller Reference Manual, Rev. 2 6-116 Freescale Semiconductor...
Page 320: Compare A Register High (Siu_Carh)
64-bit to 64-bit compare. The compare function is continuous (combinational logic — not requiring a start or stop). The compare result appears in the MATCH bit in the SIU_CCR register. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 321: Compare A Register Low (Siu_Carl)
The CMPAL field is read/write and is reset by the synchronous reset signal. Address: Base + 0x098C Access: R/W CMPAL Reset CMPAL Reset Figure 6-167. Compare A Register Low (SIU_CARL) MPC5566 Microcontroller Reference Manual, Rev. 2 6-118 Freescale Semiconductor...
Page 322: Compare B Register High (Siu_Cbrh)
Reset Figure 6-169. Compare B Register Low (SIU_CBRL) Functional Description The following sections provide a functional overview of the SIU operation. 6.4.1 System Configuration The following sections describe the system configuration. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-119...
Page 323: Boot Configuration
Data direction selection The pad configuration registers are provided to allow centralized control over external pins that are shared by more than one module. Each pad configuration register controls a single pin. MPC5566 Microcontroller Reference Manual, Rev. 2 6-120 Freescale Semiconductor...
Page 324: Reset Control
The SIU contains an overrun request for each IRQ and one combined overrun request which is the logical OR of the individual overrun requests. Only the combined overrun request is used in the device, and the individual overrun requests are not connected. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-121...
Page 325: Gpio Operation
The internal multiplexing select registers (SIU_ETISR, SIU_EIISR, and SIU_DISR) select the input source for the following components: • eQADC external trigger input signals • SIU external interrupt request signals • DSPI signals used for chaining serial and parallel DSPI modules MPC5566 Microcontroller Reference Manual, Rev. 2 6-122 Freescale Semiconductor...
Page 326: Eqadc External Trigger Input Multiplexing
All ETRIG inputs are multiplexed in the same manner. If an eTPU or eMIOS channel is selected as an ETRIG input to the eQADC, you can activate the alternate function of that eTPU or eMIOS signal on the external pin. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-123...
Page 327: Siu External Interrupt Input Multiplexing
DSPI C[1] serialized input DSPI D[2] serialized input ESEL[0] ESEL[1] NOTE: The MPC5566 has DSPI A in addition to B, C, D. Figure 6-173. DSPI Serialized Input Multiplexing 6.4.5.3 Multiplexed Inputs for DSPI Multiple Transfer Operation Each DSPI module can be combined in a serial or parallel chain (multiple transfer operation). Serial chaining allows SPI operation with an external device that has more bits than one DSPI module.
Page 328 DSPIs. The input source for each DSPI SIN, SS, SCK, and trigger signal is individually specified in the DSPI input select register (SIU_DISR). An example of a parallel chain is shown in Figure 6-174. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-125...
Page 329 System Integration Unit (SIU) DSPI C (slave) DSPI B (master) SOUT SOUT Trigger MTRIG PCS[0] SCK IN SCK IN SOUT External SPI device Figure 6-174. DSPI Serial Chaining MPC5566 Microcontroller Reference Manual, Rev. 2 6-126 Freescale Semiconductor...
Page 330 System Integration Unit (SIU) DSPI A (master) DSPI B (slave) SOUT SOUT Trigger MTRIG PCS[0] SCK IN SOUT SCK IN SCK IN SOUT External SPI device External SPI device Figure 6-175. DSPI Parallel Chaining MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 6-127...
Page 331 System Integration Unit (SIU) MPC5566 Microcontroller Reference Manual, Rev. 2 6-128 Freescale Semiconductor...
Page 332: Introduction
Table 7-1. XBAR Switch Ports Port Module Master ID Type Number e200z6 core–CPU instruction / data Master 0 e200z6–Nexus Master 0 eDMA_A Master 1 External bus interface Master 2 Master 3 MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 333: Overview
Memory” for information on accessing flash memory) — EBI — Internal SRAM — Peripheral bridge A — Peripheral bridge B • 32-bit address, 64-bit data paths • Fully concurrent transfers between independent master and slave ports MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 334: Modes Of Operation
XBAR_MPR7 Master priority register for slave port 7 Base + (0x0704–0x070F) — Reserved — Base + 0x0710 XBAR_SGPCR7 General-purpose control register for slave port 7 Base + 0x0714– — Reserved — 0x0003_FFFF MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 335: Register Descriptions
(RO) bit is set in the slave general-purpose control register, the master priority register can only be read. Attempts to write to it have no effect on the MPR and result in an error. NOTE XBAR_MPR must be written with a read/modify/write for code compatibility. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 336 Master 1 priority. Set the arbitration priority for master port 1 on the associated slave port. MSTR1 000 This master has the highest priority when accessing the slave port. 100 This master has the lowest priority when accessing the slave port. 101–111 Invalid values MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 337: Slave General-Purpose Control Registers (Xbar_Sgpcrn)
Some of the unused bits in the SGPCRn registers are writeable and readable, but they serve no function. Setting any of these bits has no effect on the operation of this module. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 338 10 LPP—Low-power park. When no master is making a request, the arbiter parks the slave port on no master and drives all slave port outputs to a safe state. 11 Invalid value MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 339: Functional Description
Outstanding request to slave port A that has a long response time • Pending access to a different slave port B • Lower priority master also makes a request to the different slave port B. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 340: Master Ports
This occurs when a handoff of bus ownership occurs and there are no wait states from the slave port. A requesting master which does not own the slave port is granted access after a one clock delay. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 341: Priority Assignment
The next master in line is granted access to the slave port when the current transfer is completed, or possibly on the next clock cycle if the current master has no pending access request. MPC5566 Microcontroller Reference Manual, Rev. 2 7-10 Freescale Semiconductor...
Page 342: Parking
However, when a master does make a request to a slave port parked in low-power-park, a one clock arbitration delay is incurred to get ownership of the slave port. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 343 Crossbar Switch (XBAR) MPC5566 Microcontroller Reference Manual, Rev. 2 7-12 Freescale Semiconductor...
Page 344: Introduction
To use the ECC for SRAM, write to SRAM memory before you enable the ECC. Refer to Section 8.3, “Initialization and Application Information.” 8.1.2 Features The ECSM includes these features: • Configurable for reporting non-correctable errors • Registers for capturing ECC information for RAM and flash access errors MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 345: Memory Map And Register Definition
The e200z6 core also provides this functionality and is the preferred method for watchdog implementation. Refer to Section 8.2.1.1, “Software Watchdog Timer Control, Service, and Interrupt Registers (ECSM_SWTCR, ECSM_SWTSR, and ECSM_SWTIR).” MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 346: Register Descriptions
RAM ECC address register (ECSM_REAR) • RAM ECC master number register (ECSM_REMR) • RAM ECC attributes register (ECSM_REAT) • RAM ECC data register (ECSM_REDR) The details of each ECC register are in the subsequent sections. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 347: Ecc Configuration Register (Ecsm_Ecr)
| ECSM_ECR[EFNCR] & ECSM_ESR[FNCE] // flash, noncorrectable error where the combination of the following criteria generates the interrupt request: • Correctly-enabled category in the ECSM_ECR; and • Condition in the ECSM_ESR detected. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 348: Ecc Error Generation Register (Ecsm_Eegr)
The ECSM_EEGR is a 16-bit control register used to generate double-bit data errors in internal SRAM. This allows you to test the software service routines for memory error logging.By generating errors during MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 349 ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM. After this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again to properly re-enable the error generation logic. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 350: Flash Ecc Address Register (Ecsm_Fear)
Section 13.3.2.7, “Address Register (FLASH_AR)” to retrieve the doubleword address. Base + 0x0050 Access: Read FEAR Reset FEAR Reset “U” signifies a bit that is uninitialized. Figure 8-4. Flash ECC Address Register (ECSM_FEAR) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 351: Flash Ecc Master Number Register (Ecsm_Femr)
ECC event in the flash memory. Depending on the state of the ECSM_ECR register, an ECC event in the flash loads the address, attributes and data of the access into the ECSM_FEAR, ECSM_FEMR, ECSM_FEAT, and ECSM_FEDR registers, and asserts the FNCE flag in ECSM_ESR. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 352: Flash Ecc Data High Register (Ecsm_Fedrh)
ECC event in flash memory. Depending on the state of the ECSM_ECR, an ECC event in the flash loads the address, attributes and data of the access into the ECSM_FEAR, ECSM_FEMR, ECSM_FEAT and ECSM_FEDR registers, and asserts the FNCE flag in ECSM_ESR. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 353: Flash Ecc Data Low Registers (Ecsm_Fedrl)
ECC event in the flash memory. Depending on the state of the ECSM_ECR, an ECC event in the flash loads the address, attributes and data of the access into the ECSM_FEAR, ECSM_FEMR, ECSM_FEAT and ECSM_FEDR registers, and asserts the FNCE flag in ECSM_ESR. MPC5566 Microcontroller Reference Manual, Rev. 2 8-10 Freescale Semiconductor...
Page 354: Ram Ecc Address Register (Ecsm_Rear)
ECSM_REDR registers, and asserts the RNCE flag in ECSM_ESR. Base + 0x0060 Access: Read REAR Reset REAR Reset “U” signifies a bit that is uninitialized. Figure 8-9. RAM ECC Address Register (ECSM_REAR) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 8-11...
Page 355: Ram Ecc Master Number Register (Ecsm_Remr)
ECC event in the RAM memory. Depending on the state of the ECSM_ECR, an ECC event in the RAM loads the address, attributes and data of the access into the ECSM_REAR, ECSM_REMR, ECSM_REAT and ECSM_REDR registers, and asserts the RNCE flag in ECSM_ESR. MPC5566 Microcontroller Reference Manual, Rev. 2 8-12 Freescale Semiconductor...
Page 356: Ram Ecc Data High Register (Ecsm_Redrh)
ECC event in the RAM memory. Depending on the state of the ECSM_ECR, an ECC event in the RAM loads the address, attributes and data of the access into the ECSM_REAR, ECSM_REMR, ECSM_REAT, ECSM_REDRH and ECSM_REDRL registers, and asserts the RFNCE flag in ECSM_ESR. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 8-13...
Page 357: Ram Ecc Data Low Registers (Ecsm_Redrl)
RAM loads the address, attributes and data of the access to the following registers: • ECSM_REAR • ECSM_REMR • ECSM_REAT • ECSM_REDRH • ECSM_REDRL and asserts the RFNCE flag in ECSM_ESR. The data captured on a multi-bit non-correctable ECC error is undefined. MPC5566 Microcontroller Reference Manual, Rev. 2 8-14 Freescale Semiconductor...
Page 358: Initialization And Application Information
8-15. When error reporting is enabled, as long as its priority is 0, an interrupt request is generated to the interrupt controller (INTC) even though the INTC request is not serviced. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 8-15...
Page 359 If the error was caused by a CPU instruction access, an instruction storage exception (IVOR3) is generated. • If vector 9 of INTC is enabled, an external exception (IVOR4) is generated. MPC5566 Microcontroller Reference Manual, Rev. 2 8-16 Freescale Semiconductor...
Page 360 The address of the corrupted instruction for an instruction storage exception (SRR0). • The address where the error occurred for a data storage exception, indicated in the data exception address register (DEAR). MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 8-17...
Page 361 Error Correction Status Module (ECSM) MPC5566 Microcontroller Reference Manual, Rev. 2 8-18 Freescale Semiconductor...
Page 362: Introduction
Program model and channel arbitration Address Control Data path path Slave read data Bus write data Bus address *n = 64 channels eDMA peripheral eDMA done request Figure 9-1. eDMA Block Diagram MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 363: Features
64-channel implementation performs complex data transfers with minimal intervention from a host processor — 32 bytes of data registers, used as temporary storage to support burst transfers (refer to SSIZE bit) — Connections to the crossbar switch for bus mastering the data movement MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 364: Modes Of Operation
If the signal asserts during a data block transfer as described by a minor loop in the current active channel’s TCD, the eDMA continues the operation until the minor loop completes. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 365: Memory Map And Register Definition
1 priority register Base + 0x0102 EDMA_CPR2 eDMA channel 2 priority register Base + 0x0103 EDMA_CPR3 eDMA channel 3 priority register Base + 0x0104 EDMA_CPR4 eDMA channel 4 priority register MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 366 34 priority register Base + 0x0123 EDMA_CPR35 eDMA channel 35 priority register Base + 0x0124 EDMA_CPR36 eDMA channel 36 priority register Base + 0x0125 EDMA_CPR37 eDMA channel 37 priority register MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 367 02 Base + 0x1060 TCD03 eDMA transfer control descriptor 03 Base + 0x1080 TCD04 eDMA transfer control descriptor 04 Base + 0x10A0 TCD05 eDMA transfer control descriptor 05 MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 368 35 Base + 0x1480 TCD36 eDMA transfer control descriptor 36 Base + 0x14A0 TCD37 eDMA transfer control descriptor 37 Base + 0x14C0 TCD38 eDMA transfer control descriptor 38 MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 369: Register Descriptions
64-bits wide. These registers are implemented as two 32-bit registers, and include an ‘H’ and ‘L’ suffixes, indicating the high and low portions of the control function. 9.2.2.1 eDMA Control Register (EDMA_CR) The 32-bit EDMA_CR defines the basic operating configuration of the eDMA. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 370 Channel group 2 priority. Group 2 priority level when fixed priority group arbitration is enabled. GRP2PRI 20–21 Channel group 1 priority. Group 1 priority level when fixed-priority group arbitration is enabled. GRP1PRI MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 371: Edma Error Status Register (Edma_Esr)
If a system bus read or write is terminated with an error, the data transfer is immediately stopped and the appropriate bus error flag is set. In this case, the state of the channel’s transfer control descriptor is updated MPC5566 Microcontroller Reference Manual, Rev. 2 9-10...
Page 372 0 No channel priority error. 1 The last recorded error was a configuration error in the channel priorities within a group, indicating not all channel priorities within a group are unique. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 9-11...
Page 373: Edma Enable Request Registers (Edma_Erqrh, Edma_Erqrl)
31–0. The state of any given channel enable is directly affected by writes to these registers; the state is also affected by writes to the EDMA_SERQR and EDMA_CERQR. The EDMA_CERQR and MPC5566 Microcontroller Reference Manual, Rev. 2 9-12 Freescale Semiconductor...
Page 374 EDMA_ERQR bit for that channel. If the TCD.D_REQ bit is set, then the corresponding EDMA_ERQR bit is cleared after the major loop is MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 375: Edma Enable Error Interrupt Registers (Edma_Eeirh, Edma_Eeirl)
Figure 9-6. eDMA Enable Error Interrupt High Register (EDMA_EEIRH) Address: Base + 0x0014 Access: User R/W R EEI Reset R EEI Reset Figure 9-7. eDMA Enable Error Interrupt Low Register (EDMA_EEIRL) MPC5566 Microcontroller Reference Manual, Rev. 2 9-14 Freescale Semiconductor...
Page 376: Edma Set Enable Request Register (Edma_Serqr)
EDMA_ERQRL to be zeroed, disabling all DMA request inputs. Reads of this register return all zeroes. Address: Base + 0x0019 Access: User W/O CERQ[0:6] Reset Figure 9-9. eDMA Clear Enable Request Register (EDMA_CERQR) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 9-15...
Page 377: Edma Set Enable Error Interrupt Register (Edma_Seeir)
EDMA_EEIRL to be zeroed, disabling error interrupts for all channels. Reads of this register return all zeroes. Address: Base + 0x001B Access: User W/O CEEI[0:6] Reset Figure 9-11. eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR) MPC5566 Microcontroller Reference Manual, Rev. 2 9-16 Freescale Semiconductor...
Page 378: Edma Clear Interrupt Request Register (Edma_Cirqr)
EDMA_ERH or EDMA_ERL to be cleared. Setting bit 1 (CERRn) provides a global clear function, forcing the entire contents of the EDMA_ERH and EDMA_ERL to be zeroed, clearing all channel error indicators. Reads of this register return all zeroes. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 9-17...
Page 379: Edma Set Start Bit Register (Edma_Ssbr)
The data value on a register write causes the DONE bit in the corresponding transfer control descriptor to be cleared. Setting bit 1 (CDSBn) provides a global clear function, forcing all DONE bits to be cleared. MPC5566 Microcontroller Reference Manual, Rev. 2 9-18 Freescale Semiconductor...
Page 380: Edma Interrupt Request Registers (Edma_Irqrh, Edma_Irqrl)
The EDMA_CIRQR is provided so the interrupt request for a single channel can easily be cleared without the need to perform a read-modify-write sequence to the EDMA_IRQRH and EDMA_IRQRL. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 9-19...
Page 381: Edma Error Registers (Edma_Erh, Edma_Erl)
Typically, a write to the EDMA_CER in the interrupt service routine is used for this purpose. Recall the normal DMA MPC5566 Microcontroller Reference Manual, Rev. 2 9-20...
Page 382 Figure 9-19. eDMA Error Low Register (EDMA_ERL) Table 9-15. EDMA_ERH, EDMA_ERL Field Descriptions Field Description 0–63 eDMA Error n. 0 An error in channel n has not occurred. ERRn 1 An error in channel n has occurred. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 9-21...
Page 383: Dma Hardware Request Status (Edma_Hrsh, Edma_Hrsl)
A hardware service request for channel n is present. Note: The hardware request status reflects the state of the request as seen by the arbitration logic. Therefore, this status is affected by the EDMA_ERQRL[ERQn] bit. MPC5566 Microcontroller Reference Manual, Rev. 2 9-22 Freescale Semiconductor...
Page 384: Edma Channel N Priority Registers (Edma_Cprn)
Enable channel preemption. 0 Channel n cannot be suspended by a higher priority channel’s service request. 1 Channel n can be temporarily suspended by the service request of a higher priority channel. Reserved MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 9-23...
Page 385: Transfer Control Descriptor (Tcd)
Each channel requires a 256-bit transfer control descriptor for defining the desired data movement operation. The channel descriptors are stored in the local memory in sequential order: channel 0, channel 1,... channel 63. The definitions of the TCD are presented as 23 variable-length fields. MPC5566 Microcontroller Reference Manual, Rev. 2 9-24 Freescale Semiconductor...
Page 386 0x1000 + (32 x n) + 254 Channel interrupt enable when current major INT_MAJ iteration count complete 0x1000 + (32 x n) + 255 Channel start START MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 9-25...
Page 387 The TCD structures for the eDMA channels shown in Figure 9-23 implemented in internal SRAM. These structures are not initialized at reset. Therefore, all channel TCD parameters must be initialized by the application code before activating that channel. MPC5566 Microcontroller Reference Manual, Rev. 2 9-26 Freescale Semiconductor...
Page 388 If the major iteration count is completed, additional processing is performed. Note: The NBYTES value of 0x0000_0000 is interpreted as 0x1_0000_0000, thus specifying a four GB transfer. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 9-27...
Page 389 BITER and CITER must be 0x0001. 176–191 DOFF Destination address signed offset. Sign-extended offset applied to the current destination 0x14 [16:31] [0:15] address to form the next-state value as each destination write is completed. MPC5566 Microcontroller Reference Manual, Rev. 2 9-28 Freescale Semiconductor...
Page 390 CITER field. Note: If the channel is configured to execute a single service request, the initial values of BITER and CITER must be 0x0001. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 9-29...
Page 391 1 The current channel’s TCD specifies a scatter gather format. The DLAST_SGA field provides a memory pointer to the next TCD to be loaded into this channel after the outer major loop completes its execution. MPC5566 Microcontroller Reference Manual, Rev. 2 9-30 Freescale Semiconductor...
Page 392 Channel start. If this flag is set, the channel is requesting service. The eDMA hardware 0x1C automatically clears this flag after the channel begins execution. [31] 0 The channel is not explicitly started. 1 The channel is explicitly started via a software initiated service request. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 9-31...
Page 393: Functional Description
‘minor loop’ byte count has been moved. MPC5566 Microcontroller Reference Manual, Rev. 2 9-32 Freescale Semiconductor...
Page 394: Edma Basic Data Flow
The TCD memory is organized 64-bits in width to minimize the time needed to fetch the activated channel’s descriptor and load it into the eDMA engine address path channel{x,y} registers. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 9-33...
Page 395 This source read/destination write processing continues until the inner minor byte count has been transferred. The eDMA Done Handshake signal is asserted at the end of the minor byte count transfer. MPC5566 Microcontroller Reference Manual, Rev. 2 9-34 Freescale Semiconductor...
Page 396 TCD from memory using the scatter/gather address pointer included in the descriptor. The updates to the TCD memory and the assertion of an interrupt request are shown in Figure 9-26. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 9-35...
Page 397: Edma Performance
Internal SRAM can be accessed with zero wait-states when viewed from the system bus data phase. • All slave reads require two wait-states, and slave writes three wait-states, again viewed from the system bus data phase. • All slave accesses are 32-bits in size. MPC5566 Microcontroller Reference Manual, Rev. 2 9-36 Freescale Semiconductor...
Page 398 The first two parts of the activated channel’s TCD is read from the local memory. The memory width to the eDMA engine is 64 bits, so the entire descriptor can be accessed in four cycles. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 9-37...
Page 399 A general formula to compute the peak request rate (with overlapping requests) is: PEAKreq = freq / [entry + (1 + read_ws) + (1 + write_ws) + exit] where: PEAKreq – peak request rate freq – system frequency MPC5566 Microcontroller Reference Manual, Rev. 2 9-38 Freescale Semiconductor...
Page 400: Initialization And Application Information
1. Write the EDMA_CR if a configuration other than the default is desired. 2. Write the channel priority levels into the EDMA_CPRn registers if a configuration other than the default is desired. 3. Enable error interrupts in the EDMA_EEIRL and/or EDMA_EEIRH registers (optional). MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 9-39...
Page 401 DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (biter). MPC5566 Microcontroller Reference Manual, Rev. 2 9-40 Freescale Semiconductor...
Page 402: Dma Programming Errors
The eDMA performs various tests on the transfer control descriptor to verify consistency in the descriptor data. Most programming errors are reported on a per channel basis with the exception of two errors: group priority error and channel priority error, or EDMA_ESR[GPE] and EDMA_ESR[CPE], respectively. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 9-41...
Page 403: Dma Request Assignments
EQADC.FISR1[RFDF1] eQADC Receive FIFO 1 Drain Flag eQADC_FISR2_CFFF2 EQADC.FISR2[CFFF2] eQADC Command FIFO 2 Fill Flag eQADC_FISR2_RFDF2 EQADC.FISR2[RFDF2] eQADC Receive FIFO 2 Drain Flag eQADC_FISR3_CFFF3 EQADC.FISR3[CFFF3] eQADC Command FIFO 3 Fill Flag MPC5566 Microcontroller Reference Manual, Rev. 2 9-42 Freescale Semiconductor...
Page 404 DSPIA.SR[RFDF] DSPIA Receive FIFO Drain Flag eSCIB_COMBTX ESCIB.SR[TDRE] || eSCIB combined DMA request of the Transmit Data ESCIB.SR[TC] || Register Empty, Transmit Complete, and LIN Transmit ESCIB.SR[TXRDY] Data Ready DMA requests MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 9-43...
Page 405 Channel 28 Data Transfer Request Status eTPU_CDTRSR_B_DTRS29 ETPU.CDTRSR_B[DTRS29] eTPUB Channel 29 Data Transfer Request Status eTPU_CDTRSR_B_DTRS30 ETPU.CDTRSR_B[DTRS30] eTPUB Channel 30 Data Transfer Request Status eTPU_CDTRSR_B_DTRS31 ETPU.CDTRSR_B[DTRS31] eTPUB Channel 31 Data Transfer Request Status MPC5566 Microcontroller Reference Manual, Rev. 2 9-44 Freescale Semiconductor...
Page 406: Dma Arbitration Mode Considerations
This scenario ensures that all channels are guaranteed service at some point, regardless of the request rates. However, the potential latency can be quite high. All channels are treated equally. Priority levels are not used in round-robin/round-robin mode. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 9-45...
Page 407: Fixed-Group Arbitration, Round-Robin Channel Arbitration
All other TCD fields = 0 This generates the following sequence of events: 1. Slave write to the TCD.START bit requests channel service. 2. The channel is selected by arbitration for servicing. MPC5566 Microcontroller Reference Manual, Rev. 2 9-46 Freescale Semiconductor...
Page 408: Multiple Requests
TCD.DADDR = 0x2000 TCD.DOFF = 4 TCD.DSIZE = 2 TCD.DLAST_SGA= –32 TCD.INT_MAJ = 1 TCD.START = 0 (Initialize all other fields before writing this bit.) All other TCD fields = 0 MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 9-47...
Page 409 TCD.CITER = 2 (TCD.BITER). 15. eDMA engine writes: TCD.ACTIVE = 0, TCD.DONE = 1, EDMA_IRQRn = 1. 16. The channel retires -> major loop complete. The eDMA goes idle or services the next channel. MPC5566 Microcontroller Reference Manual, Rev. 2 9-48 Freescale Semiconductor...
Page 410: Modulo Feature
The best method to test for minor loop completion when using hardware initiated service requests is to read the TCD.CITER field and test for a change. The hardware request and acknowledge handshakes signals are not visible in the programmer’s model. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 9-49...
Page 411: Active Channel Tcd Reads
The TCD.CITER.E_LINK field are used to determine whether a minor loop link is requested. When enabled, the channel link is made after each iteration of the minor loop except for the last. MPC5566 Microcontroller Reference Manual, Rev. 2 9-50...
Page 412 Link channel number when linking at end of minor loop (current iteration) Link at end of major.e_link Enable channel-to-channel linking on major loop Major Loop completion major.linkch Link channel number when linking at end of major loop MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 9-51...
Page 413: Dynamic Programming
TCD after that channel’s TCD.DONE bit is set indicating the major loop is complete. NOTE The user must clear the TCD.DONE bit before writing the TCD.MAJOR.E_LINK or TCD.E_SG bits. The TCD.DONE bit is cleared automatically by the eDMA engine after a channel begins execution. MPC5566 Microcontroller Reference Manual, Rev. 2 9-52 Freescale Semiconductor...
Page 414: Introduction
Although N (largest addressable IRQ vector number) = 329, this does not indicate the total number of interrupts available on this device. The total number of available interrupts on this device is 332: 298 peripheral IRQs, eight software-configurable IRQs, and 16 reserved. Figure 10-1. INTC Block Diagram MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 10-1...
Page 415: Overview
Table 10-1. Interrupt Sources Available Number of Interrupt Source (IRQs) Interrupts Available Software Watchdog Memory eDMA FMPLL External IRQ input pins eMIOS eTPU engine A eTPU engine B eQADC DSPI eSCI FlexCAN MPC5566 Microcontroller Reference Manual, Rev. 2 10-2 Freescale Semiconductor...
Page 416 Because the memory is mapped in four-byte words, the total number of interrupt vectors must be a multiple of four: • If the total number of available interrupts is not a multiple of four, additional interrupt vectors exist up to the next four-byte boundary. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 10-3...
Page 417: Features
ISR can assert a software settable interrupt request to finish the servicing in a lower priority ISR. 10.1.3 Features Features include the following: • Total number of interrupt vectors is 332 , of which: — 298 are peripheral interrupt vectors — 8 are software settable sources MPC5566 Microcontroller Reference Manual, Rev. 2 10-4 Freescale Semiconductor...
Page 418: Modes Of Operation
16 reserved. Because the memory is mapped in four-byte words, the total number of interrupt vectors must be a multiple of four, therefore additional interrupt vectors exist to complete the word. This results in a total of 332 interrupt vectors. However, interrupt vectors 330–332 are reserved and not available. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 10-5...
Page 419: Hardware Vector Mode
INTC_IACKR[INTVEC]. Each interrupt exception handler address is aligned on a four-word (16-byte) boundary. IVOR4 is not used in this mode, and software does not need to read INTC_IACKR to get the interrupt vector number. MPC5566 Microcontroller Reference Manual, Rev. 2 10-6 Freescale Semiconductor...
Page 420: External Signal Description
Table 10-2. External Interrupt Signals Reset Post Reset Function P/A/G Description Function/ Function/ Type State State EMIOS[14]_ eMIOS channel — / WKPCFG — / WKPCFG IRQ[0]_ External interrupt request CNTXD CAN D transmit GPIO[193] GPIO MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 10-7...
Page 421 For each pin in the table, each line in the function column is a separate function muxed to the pin. For all device I/O pins, the selection of a primary, secondary or tertiary function is done in the SIU module except where explicitly noted. MPC5566 Microcontroller Reference Manual, Rev. 2 10-8...
Page 422: Intc_Cpr
When the HVEN bit in the INTC_MCR is asserted, a read of the INTC_IACKR has no side effects. The PRI fields are “Reserved” for peripheral interrupt requests whose vectors are labeled as Reserved in Table 10-9. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 10-9...
Page 423: Register Descriptions
Hardware vector enable. Controls whether the INTC is in hardware vector mode or software vector mode. Refer to HVEN Section 10.1.4, “Modes of Operation”, for the details of the handshaking with the processor in each mode. 0 Software vector mode 1 Hardware vector mode MPC5566 Microcontroller Reference Manual, Rev. 2 10-10 Freescale Semiconductor...
Page 424: Intc Current Priority Register (Intc_Cpr)
The reading also pushes the PRI value in the INTC current priority register (INTC_CPR) onto the LIFO and updates PRI in the INTC_CPR with the priority of the interrupt request. The side effect MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 425 Vector table base address. Can be the base address of a vector table of addresses of ISRs. The VTBA only uses 0–19 the left-most 20 bits when the VTES bit in INTC_MCR is asserted. VTBA MPC5566 Microcontroller Reference Manual, Rev. 2 10-12 Freescale Semiconductor...
Page 426: Intc End-Of-Interrupt Register (Intc_Eoir)
32-bit boundary. Address: Base + 0x0020 + n (INTC_SSCIRn); n = 0–7 Access: R/W CLRn SETn Reset Figure 10-12. INTC Software Set/Clear Interrupt Register (INTC_SSCIRn) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 10-13...
Page 427: Intc Priority Select Registers (Intc_Psr0–329)
Description 0–3 Reserved, must be cleared. 4–7 Priority select. Selects the priority for corresponding interrupt request. PRIn 1111 Priority 15 (highest) 1110 Priority 14 0001 Priority 1 0000 Priority 0 (lowest) MPC5566 Microcontroller Reference Manual, Rev. 2 10-14 Freescale Semiconductor...
Page 428: Functional Description
The Source column shows the C language syntax for the register bit label: module_register[bit]. Interrupt requests from the same module location are ORed together. The individual interrupt priorities are selected in INTC_PSRn, where the priority select register is assigned according to the vector number. Table 10-9. MPC5566 Interrupt Request Sources Hardware Vector...
Page 429 Interrupt Controller (INTC) Table 10-9. MPC5566 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset 0x0130 EDMA_IRQRL[INT08] eDMA channel interrupt 8 0x0140 EDMA_IRQRL[INT09] eDMA channel interrupt 9 0x0150 EDMA_IRQRL[INT10] eDMA channel interrupt 10 0x0160 EDMA_IRQRL[INT11] eDMA channel interrupt 11...
Page 430 Interrupt Controller (INTC) Table 10-9. MPC5566 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset 0x0300 SIU_EISR[EIF2] SIU external interrupt flag 2 0x0310 SIU_EISR[EIF3] SIU external interrupt flag 3 0x0320 SIU_EISR[EIF15:EIF4] SIU external interrupt flags 15–4 eMIOS...
Page 431 Interrupt Controller (INTC) Table 10-9. MPC5566 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset 0x04B0 ETPU_CISR_A[CIS7] eTPU engine A channel 7 interrupt status 0x04C0 ETPU_CISR_A[CIS8] eTPU engine A channel 8 interrupt status 0x04D0 ETPU_CISR_A[CIS9] eTPU engine A channel 9 interrupt status...
Page 432 Interrupt Controller (INTC) Table 10-9. MPC5566 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset 0x0670 EQADC_FISR0[EOQF] eQADC command FIFO 0 command queue end-of-queue flag 0x0680 EQADC_FISR0[CFFF] eQADC command FIFO 0 fill flag 0x0690 EQADC_FISR0[RFDF] eQADC receive FIFO 0 drain flag...
Page 433 Interrupt Controller (INTC) Table 10-9. MPC5566 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset DSPI B, C, and D 0x0830 DSPI B combined overrun interrupt requests: DSPI_BSR[TFUF] • Transmit FIFO underflow DSPI_BSR[RFOF] • Receive FIFO overflow...
Page 434 Interrupt Controller (INTC) Table 10-9. MPC5566 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset eSCI 0x0920 Combined interrupt requests of eSCI Module A: • LIN status register 1 • LIN status register 2 • SCI status register 2 ESCIA_SR[TDRE] •...
Page 435 Interrupt Controller (INTC) Table 10-9. MPC5566 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset FlexCAN A and FlexCAN C 0x0980 CANA_ESR[BOFF_INT] FlexCAN A bus off interrupt CANA_ESR[TWRN_INT] FlexCAN A transmit warning interrupt CANA_ESR[RWRN_INT] FlexCAN A receive warning interrupt...
Page 436 Interrupt Controller (INTC) Table 10-9. MPC5566 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset 0x0B40 CANC_IFRL[BUF4] FlexCAN C buffer 4 interrupt 0x0B50 CANC_IFRL[BUF5] FlexCAN C buffer 5 interrupt 0x0B60 CANC_IFRL[BUF6] FlexCAN C buffer 6 interrupt 0x0B70...
Page 437 Interrupt Controller (INTC) Table 10-9. MPC5566 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset 0x0CE0 EMIOS_GFR[F20] eMIOS channel 20 flag 0x0CF0 EMIOS_GFR[F21] eMIOS channel 21 flag 0x0D00 EMIOS_GFR[F22] eMIOS channel 22 flag 0x0D10 EMIOS_GFR[F23] eMIOS channel 23 flag...
Page 438 Interrupt Controller (INTC) Table 10-9. MPC5566 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset 0x0EC0 EDMA_IRQRH[INT57] eDMA channel interrupt 57 0x0ED0 EDMA_IRQRH[INT58] eDMA channel interrupt 58 0x0EE0 EDMA_IRQRH[INT59] eDMA channel interrupt 59 0x0EF0 EDMA_IRQRH[INT60] eDMA channel interrupt 60...
Page 439 Interrupt Controller (INTC) Table 10-9. MPC5566 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset 0x10A0 ETPU_CISR_B[CIS23] eTPU engine B channel 23 interrupt status 0x10B0 ETPU_CISR_B[CIS24] eTPU engine B channel 24 interrupt status 0x10C0 ETPU_CISR_B[CIS25] eTPU engine B channel 25 interrupt status...
Page 440 Interrupt Controller (INTC) Table 10-9. MPC5566 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset 0x1250 CANB_IFRL[BUF10] FlexCAN B buffer 10 interrupt 0x1260 CANB_IFRL[BUF11] FlexCAN B buffer 11 interrupt 0x1270 CANB_IFRL[BUF12] FlexCAN B buffer 12 interrupt 0x1280...
Page 441: Peripheral Interrupt Requests
Interrupt Controller (INTC) Table 10-9. MPC5566 Interrupt Request Sources (continued) Hardware Vector Vector Mode Source Description Number Offset 0x1480 CAND_IFRH[BUF63:BUF32] FlexCAN D buffers 63–32 interrupts 0x1490–0x14B0 329–331 Reserved The vector number is used to identify the interrupt priority select register; it does not indicate the maximum number of usable interrupt sources.
Page 442: Unique Vector For Each Interrupt Request Source
If multiple interrupt requests from the priority arbitrator submodule are asserted, then only the one with the lowest vector is passed as asserted to the vector encoder submodule. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 443: Vector Encoder Submodule
Therefore, although a priority of 0 was overwritten, it is regenerated with the popping of an empty LIFO. The LIFO is not memory mapped. MPC5566 Microcontroller Reference Manual, Rev. 2 10-30 Freescale Semiconductor...
Page 444: Details On Handshaking With Processor
This next instruction is part of the preempted ISR or the interrupt exception handler’s prolog or epilog. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 10-31...
Page 445: Read Intc_Iackr
The handshaking near the end of the interrupt exception handler, that is the writing to the INTC_EOIR, is the same as in software vector mode. Refer to Section 10.4.3.1.2, “End-of-Interrupt Exception Handler.” MPC5566 Microcontroller Reference Manual, Rev. 2 10-32 Freescale Semiconductor...
Page 446: Initialization And Application Information
PRI in INTC_CPR to zero enable processor recognition of interrupts 10.5.2 Interrupt Exception Handler These example interrupt exception handlers use Power Architecture assembly code. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 10-33...
Page 447: Software Vector Mode
ISR for interrupt with vector 510 address of ISR for interrupt with vector 511 ISRx: code to service the interrupt event code to clear flag bit which drives interrupt request to INTC # return to epilog MPC5566 Microcontroller Reference Manual, Rev. 2 10-34 Freescale Semiconductor...
Page 448: Hardware Vector Mode
If a task shares a resource with an ISR and the PCP is being used to manage that shared resource, then the task’s priority can be elevated in the INTC_CPR while the shared resource is being accessed. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 449: Order Of Execution
INTC_EOIR. Interrupt taken. ISR208 starts to execute, even though peripheral interrupt request 300 asserted first. ISR208 completes. Interrupt exception handler writes to INTC_EOIR. Interrupt taken. ISR308 starts to execute. MPC5566 Microcontroller Reference Manual, Rev. 2 10-36 Freescale Semiconductor...
Page 450: Priority Ceiling Protocol
ISR1 and ISR2 writes to execute while the processor responds to the INTC request, discards the transactions, and flushes the processing pipeline. However, ISR2 cannot access the data block coherently because the data block is now corrupted. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 10-37...
Page 451: And Deadlines
Therefore, executing this later portion which does not need to be executed at this higher priority can prevent the execution of ISRs which do not have a higher priority MPC5566 Microcontroller Reference Manual, Rev. 2 10-38...
Page 452: Scheduling An Isr On Another Processor
LIFO can support. Therefore, through its use of the LIFO the INTC does not support lowering the current priority within an ISR as a way to avoid preemptive scheduling inefficiencies. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 10-39...
Page 453: Negating An Interrupt Request Outside Of Its Isr
LIFO contents provides a coherent view of the preempted priorities. The code sequence is: pop_lifo: store to INTC_EOIR load INTC_CPR, examine PRI, and store onto stack if PRI is not zero or value when interrupts were enabled, branch to pop_lifo MPC5566 Microcontroller Reference Manual, Rev. 2 10-40 Freescale Semiconductor...
Page 454: Intc_Cpr
However, since the peripheral or software settable interrupt requests are not cleared, the peripheral interrupt request to the processor re-asserts when INTC_CPR[PRI] is lower than the priorities of those peripheral or software settable interrupt requests. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 10-41...
Page 455 Interrupt Controller (INTC) MPC5566 Microcontroller Reference Manual, Rev. 2 10-42 Freescale Semiconductor...
Page 456: Introduction
Figure 11-3, “FMPLL External Reference Mode” • Figure 11-4, “FMPLL Crystal Reference Mode Without FM” • Figure 11-5, “FMPLL Crystal Reference Mode With FM” • Figure 11-6, “FMPLL Dual-Controller (1:1) Mode” MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 11-1...
Page 457: Fmpll And Clock Architecture
MDIS CAN interface CLK FlexCAN MDIS Message buffer CLK Core, INTC, eDMA, SIU, BAM, CLK_SRC RAMs, eQADC, flash, XBAR, PBRIDGE_A, PBRIDGE_B eSCI MDIS Figure 11-1. FMPLL Block and Clock Architecture MPC5566 Microcontroller Reference Manual, Rev. 2 11-2 Freescale Semiconductor...
Page 458: Fmpll Bypass Mode
MDIS eTPU engines MDIS CAN interface CLK FlexCAN MDIS Message buffer CLK Core, INTC, eDMA, SIU, BAM, CLK_SRC RAMs, eQADC, Flash, XBAR, PBRIDGE_A, PBRIDGE_B eSCI MDIS Figure 11-2. FMPLL Bypass Mode MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 11-3...
Page 459: Fmpll External Reference Mode
MDIS CAN interface CLK FlexCAN MDIS Message buffer CLK Core, INTC, eDMA, SIU, BAM, CLK_SRC RAMs, eQADC, Flash, XBAR, PBRIDGE_A, PBRIDGE_B eSCI MDIS Figure 11-3. FMPLL External Reference Mode MPC5566 Microcontroller Reference Manual, Rev. 2 11-4 Freescale Semiconductor...
Page 460: Fmpll Crystal Reference Mode Without Fm
MDIS CAN interface CLK FlexCAN MDIS Message buffer CLK Core, INTC, eDMA, SIU, BAM, CLK_SRC RAMs, eQADC, Flash, XBAR, PBRIDGE_A, PBRIDGE_B eSCI MDIS Figure 11-4. FMPLL Crystal Reference Mode without FM MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 11-5...
Page 461: Fmpll Crystal Reference Mode With Fm
MDIS CAN interface CLK FlexCAN MDIS Message buffer CLK Core, INTC, eDMA, SIU, BAM, CLK_SRC RAMs, eQADC, Flash, XBAR, PBRIDGE_A, PBRIDGE_B eSCI MDIS Figure 11-5. FMPLL Crystal Reference Mode with FM MPC5566 Microcontroller Reference Manual, Rev. 2 11-6 Freescale Semiconductor...
Page 462: Fmpll Dual-Controller Mode (1:1)
MDIS CAN Interface CLK FlexCAN MDIS Message buffer CLK Core, INTC, eDMA, SIU, BAM, CLK_SRC RAMs, eQADC, Flash, XBAR, PBRIDGE_A, PBRIDGE_B eSCI MDIS Figure 11-6. FMPLL Dual Controller (1:1) Mode MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 11-7...
Page 463: Overview
(INTC),” for details. — User-selectable ability to generate a system reset upon loss of clock Refer to Chapter 4, “Reset,” for details. • Self-clocked mode (SCM) operation in event of input clock failure MPC5566 Microcontroller Reference Manual, Rev. 2 11-8 Freescale Semiconductor...
Page 464: Fmpll Modes Of Operation
The external support circuitry for the crystal oscillator is shown in Figure 11-7. Example component values are shown as well. Review the actual circuit with the crystal manufacturer. A block diagram illustrating crystal reference mode is shown in Figure 11-4. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 11-9...
Page 465: External Reference Mode
To enter external reference mode, the default FMPLL configuration must be overridden by following the procedure outlined in Section 11.1.4, “FMPLL Modes of Operation.” A block diagram illustrating external reference mode is shown in Figure 11-3. MPC5566 Microcontroller Reference Manual, Rev. 2 11-10 Freescale Semiconductor...
Page 466: Bypass Mode
When configured for dual-controller mode, the CLKOUT clock divider on the slave device must not be changed from its reset state of divide-by-two. Increasing or decreasing this divide ratio produces unpredictable results from the FMPLL. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 11-11...
Page 467: External Signal Description
FMPLL_SYNCR[MFD], and the read to check the lock status shown by FMPLL_SYNSR[LOCK]. Buffered writes to the FMPLL, as controlled by PBRIDGE_A_OPACR[BW0], must be disabled. MPC5566 Microcontroller Reference Manual, Rev. 2 11-12 Freescale Semiconductor...
Page 468 4–20 MHz. Refer to the device Data Sheet for F prediv values. Note: To use the 8–20 MHz OSC, the PLL predivider must be configured for divide-by-two operation by tying PLLCFG[2] low (set PREDIV to 0b000). MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 11-13...
Page 469 Selection” for more information. In bypass mode, this bit has no effect. LOCEN does not affect the loss of lock circuitry. 0 Loss of clock disabled. 1 Loss of clock enabled. MPC5566 Microcontroller Reference Manual, Rev. 2 11-14 Freescale Semiconductor...
Page 470 (PREDIV +1) × 40] ref_ext Note: To prevent unintentional interrupt requests, clear LOLIRQ before changing RATE. Note: F must be between 100–250 MHz. Refer to Section 11.4.3.2, “Programming System Clock Frequency with Frequency Modulation.” MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 11-15...
Page 471: Synthesizer Status Register (Fmpll_Synsr)
Section 11.1.4, “FMPLL Modes of Operation,” for more information.) Reset state determined during reset. Note: “w1c” signifies that this bit is cleared by writing a 1 to it. Figure 11-9. Synthesizer Status Register (FMPLL_SYNSR) MPC5566 Microcontroller Reference Manual, Rev. 2 11-16 Freescale Semiconductor...
Page 472 Chapter 4, “Reset,” for details on how to configure the system clock mode during reset. Refer to Table 11-1 for more information. 0 Dual-controller mode. 1 Crystal reference or external reference mode. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 11-17...
Page 473 FMPLL. If operating in bypass mode, LOCK remains cleared after reset. Refer to the frequency as defined in the MPC5566 Microcontroller Data Sheet for the lock/unlock range. 0 PLL is unlocked.
Page 474: Functional Description
The MCU has been designed so that the oscillator clock can be selected as the clock source for the CAN interface in the FlexCAN blocks resulting in very low jitter performance. Figure 11-1 shows a block diagram of the FMPLL and the system clock architecture. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 11-19...
Page 475: Software Controlled Power Management/Clock Gating
Each of the CLKOUT, MCKO, and ENGCLK dividers provides a nominal 50% duty cycle clock to an output pin. There is no guaranteed phase relationship between CLKOUT, MCKO, and ENGCLK. ENGCLK is not synchronized to any I/O pins. MPC5566 Microcontroller Reference Manual, Rev. 2 11-20 Freescale Semiconductor...
Page 476: External Bus Clock (Clkout)
Chapter 22, “FlexCAN2 Controller Area Network” for more information on the FlexCAN modules. 11.4.1.3.5 FEC Clocks The FEC TX_CLK and FEC_RX_CLK are inputs. An external source provides the clocks to these pins. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 11-21...
Page 477: Clock Operation
After the FMPLL acquires lock after reset, the FMPLL_SYNSR[LOCK] and FMPLL_SYNSR[LOCKS] status bits are set. If the MFD is changed or if an unexpected loss of lock condition occurs, the LOCK and MPC5566 Microcontroller Reference Manual, Rev. 2 11-22 Freescale Semiconductor...
Page 478: Fmpll Loss-Of-Lock Reset
If the FMPLL clocks have failed, the FMPLL transitions the system clock source to the reference clock. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 11-23...
Page 479: Loss-Of-Clock Reset
MFD, RFD, and PREDIV reset values. Refer to Section 11.3.1.1, “Synthesizer Control Register (FMPLL_SYNCR).” The frequency multiplier is determined by the RFD, PREDIV, and multiplication frequency divisor (MFD) bits in FMPLL_SYNCR. MPC5566 Microcontroller Reference Manual, Rev. 2 11-24 Freescale Semiconductor...
Page 480: Programming System Clock Frequency Without Frequency Modulation
ΔF NOTE Following these steps produces immediate changes in supply current, therefore make sure the power supply is decoupled with low ESR capacitors. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 11-25...
Page 481 The last step changes the RFD to get the desired final frequency. MPC5566 Microcontroller Reference Manual, Rev. 2 11-26 Freescale Semiconductor...
Page 482: Programming System Clock Frequency With Frequency Modulation
Clear FMPLL_SYNCR[LOLRE]. If this bit is set, the MCU goes into reset when MFD is written. c) Initialize the FMPLL for less than the desired final frequency: — Disable LOLIRQ. — Write FMPLL_SYNCR[PREDIV] to the desired final value. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 11-27...
Page 483 For example, if a 5% accurate supply voltage is used, then a 5% modulation depth error results. If the crystal oscillator frequency is skewed from 8 MHz, the resulting modulation frequency is proportionally MPC5566 Microcontroller Reference Manual, Rev. 2 11-28...
Page 484: Fm Calibration Routine
EXP field must be set at: Rounding this value to the closest integer yields 48, which is entered into the EXP field for this example. Table 11-10. Multiplied Factor Dividers with M Values 0–2 3–5 MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 11-29...
Page 485 After the last decision is made, the CALDONE bit of the SYNSR is written to a one. If an error occurs during the calibration routine, then CALPASS is immediately written to a zero. If the routine completed successfully then CALPASS remains a one. MPC5566 Microcontroller Reference Manual, Rev. 2 11-30 Freescale Semiconductor...
Page 486 Expected Error Count 0 (EXP) (ERR) Reference counter Control counter A – B = Delta count C–D = Error count Figure 11-11. FM Auto-Calibration Data Flow MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 11-31...
Page 487 For MFD = 21 to 31: M = 160 DIFF > 0 PCALPASS = 0 Let ERR = DIFF ERR > 0 CAL[N] = 0 Figure 11-12. FM Auto-Calibration Flow Chart MPC5566 Microcontroller Reference Manual, Rev. 2 11-32 Freescale Semiconductor...
Page 488: Introduction
See the last two columns in the table for a list of available signals on the 416 package and the VertiCal assembly. The VertiCal assembly has ball connections for all the available signals on the device. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-1...
Page 489: Overview
External Bus Interface (EBI) The following figure shows the MPC5566 EBI block diagram on the 416 package. The BR, BG, and BB signals are used for arbitration on the external bus: CLKOUT driver CLKOUT CS[0:3] External Bus ADDR[6:31] Interface DATA[0:31]...
Page 490: Features
Address bus is 32-bit with transfer size indication • 32-bit internal address bus with transfer size indication; Table 12-1 shows the address bus packages supported. Table 12-1. Address Bus Sizes in MPC5566 MPC5566 Packaging EBI Address Bus Size 24 bit 20 bit Calibration Address Bus Size...
Page 491: Modes Of Operation
EXTM = 1 and MDIS = 0 in the EBI_MCR register. The MPC5566 has arbitration pins (BB, BR, BG), therefore dual-master operation (multiple masters initiating external bus cycles) is supported. A multi-MCU system with one master and one slave is supported.
Page 492: Module Disable Mode
(16-bit) burst for both reads and writes. Except for chip-select (CS[n]) data transmissions, all data transmissions that are not 32 bits are supported in standard non-burst fashion. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-5...
Page 493: Debug Mode
Output Clockout Enabled CS[0:3] Output Chip selects DATA[0:31] Data bus Output Output enable RD_WR Read/write Transfer acknowledge Transfer error acknowledge Transfer start WE/BE[0:3] Output Write/byte enables TSIZ[0:1] Transfer size Bus busy MPC5566 Microcontroller Reference Manual, Rev. 2 12-6 Freescale Semiconductor...
Page 494: Detailed Signal Descriptions
External Bus Interface (EBI) Table 12-3. MPC5566 Signal Properties (continued) Signal Name I/O Type Function Pull Package Assembly Bus grant Bus request This column shows which signals require a weak pullup or pulldown. The EBI module does not configure the pullup or pulldown mechanisms;...
Page 495: Burst Data In Progress (Bdip)
RD_WR is driven in the same clock as the assertion of TS and valid address, and is kept valid until the cycle is terminated. During a calibration bus access, RD_WR reflects the same value as the CAL_RD_WR signal. MPC5566 Microcontroller Reference Manual, Rev. 2 12-8 Freescale Semiconductor...
Page 496: Transfer Acknowledge (Ta)
The WE/BE signals are driven by the EBI or an external master depending on the module that controls the external bus. The VertiCal assembly and the 416 BGA package use WE/BE[0:3]. During a calibration bus access, the WE/BE signals are held negated. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-9...
Page 497: Bus Busy (Bb)
The EBI negates BR as soon as it is granted the bus and the bus is not busy, provided it has no other internal requests pending. If more requests are pending, the EBI keeps BR asserted as long as needed. MPC5566 Microcontroller Reference Manual, Rev. 2 12-10...
Page 498: Transfer Size 0 Through 1 (Tsiz[0:1])
TS and CS signals are held negated on the non-calibration bus during calibration accesses, no transfer occurs on the EBI. During an EBI bus access, the calibration bus signals (other than CAL_DATA) are held in a negated state. CAL_DATA is not driven during non-calibration accesses. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-11...
Page 499: Signal Function And Direction By Mode
Calibrate the write/byte enables (output) non-EBI function Non-EBI function Bus Busy (I/O) non-EBI function Non-EBI function Bus Grant (I/O) non-EBI function Non-EBI function Bus Request (I/O) TSIZ[0:1] non-EBI function Transfer Size (Output) Transfer Size (I/O) MPC5566 Microcontroller Reference Manual, Rev. 2 12-12 Freescale Semiconductor...
Page 500: Memory Map And Register Definition
EBI base register bank 3 Base + 0x002C EBI_OR3 EBI option register bank 3 Base + 0x0058 EBI_CAL_BR3 EBI calibration base register bank 3 Base + 0x005C EBI_CAL_OR3 EBI calibration option register bank 3 MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-13...
Page 501: Register Descriptions
The EBI_MCR contains bits that configure various attributes associated with EBI operation. Base (0xC3F8_4000) Access: R/W SIZE SIZEN Reset ACGE EXTM EARB EARP MDIS Reset Figure 12-2. EBI Module Configuration Register (EBI_MCR) MPC5566 Microcontroller Reference Manual, Rev. 2 12-14 Freescale Semiconductor...
Page 502 Section 12.4.2.8.2, “Internal Bus Arbiter,” for the internal and external priority detailed description. 00 MCU has priority 01 Equal priority, round robin used 10 External master has priority 11 Invalid value 21–24 Reserved. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-15...
Page 503: Ebi Transfer Error Status Register (Ebi_Tesr)
This register is not writable in module disable mode due to the use of power saving clock modes. Base + 0x0008 Access: R/W1c Reset TEAF BMTF Reset Figure 12-3. EBI Transfer Error Status Register (EBI_TESR) MPC5566 Microcontroller Reference Manual, Rev. 2 12-16 Freescale Semiconductor...
Page 504: Ebi Bus Monitor Control Register (Ebi_Bmcr)
Bus monitor timing. Defines the timeout period, in 8 external bus clock resolution, for the bus monitor. See BMT[0:7] Section 12.4.1.7, “Bus Monitor,” for more details on bus monitor operation. × 2 + (8 BMT) Timeout period --------------------------------------------------------------------------- - External bus clock frequency MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-17...
Page 505: Ebi Base Registers 0–3 (Ebi_Brn And Ebi Calibration Base Registers 0–3 (Ebi_Cal_Brn)
Base + 0x0040 (EBI_CAL_BR0) Base + 0x0048 (EBI_CAL_BR1) Base + 0x0050 (EBI_CAL_BR2) Base + 0x0058 (EBI_CAL_BR3) Reset WEBS TBDIP Reset Figure 12-5. EBI Base Registers 0–3 (EBI_BRn) and EBI Calibration Base Registers 0–3 (EBI_CAL_BRn) MPC5566 Microcontroller Reference Manual, Rev. 2 12-18 Freescale Semiconductor...
Page 506 1 This bank is valid. In the case where EBI_MCR[DBM] is set for 16-bit data bus mode, the PS bit value is forced to one (16-bit port) and the actual value is ignored. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-19...
Page 507: Ebi Option Registers 0–3 (Ebi_Orn) And Ebi Calibration Option Registers
Values range from 0 to 15. This is the main parameter for determining the length of the cycle. • The total cycle length for the first beat (including the TS cycle): (2 + SCY) external clock cycles Section 12.5.3.1, “Example Wait State Calculation”. Reserved. MPC5566 Microcontroller Reference Manual, Rev. 2 12-20 Freescale Semiconductor...
Page 508: Functional Description
The EBI allows an external master to access internal address space when the EBI is configured for external master mode in the EBI_MCR. External master operations are described in detail in Section 12.4.2.10, “Bus Operation in External Master Mode.” MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-21...
Page 509: Memory Controller With Support For Various Memory Types
See the following sections for a full description of all chip select attributes: • Section 12.3.1.6, “EBI Base Registers 0–3 (EBI_BRn) and EBI Calibration Base Registers 0–3 (EBI_CAL_BRn)” • Section 12.3.1.7, “EBI Option Registers 0–3 (EBI_ORn) and EBI Calibration Option Registers 0–3 (EBI_CAL_ORn)” MPC5566 Microcontroller Reference Manual, Rev. 2 12-22 Freescale Semiconductor...
Page 510: Burst Support (Wrapped Only)
BMTF bit is set in the EBI_TESR. The timeout period is measured in external bus (CLKOUT) cycles. Thus the effective real-time period is multiplied (by two or four) when a configurable bus speed mode is used, even though the BMT field itself is unchanged. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-23...
Page 511: Port Size Configuration Per Chip Select (16 Or 32 Bits)
The write/byte enable lines affected in a transaction for a 32-bit port (PS = 0) and a 16-bit port (PS = 1) are shown in Table 12-13. Only big endian byte ordering is supported by the EBI. MPC5566 Microcontroller Reference Manual, Rev. 2 12-24 Freescale Semiconductor...
Page 512: Configurable Bus Speed Clock Modes
MPC5xx parts that the user needs to be aware of before assuming that an MPC5xx-compatible device works with this EBI. See Section 12.5.5, “Summary of Differences from MPC5xx,” for details. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-25...
Page 513: Misaligned Access Support
For example, a halfword write to 0×0003 (misaligned case #4) with 16-bit port size results in four external 16-bit transfers because of the transfer granularity of 32 bits. For MPC5566 Microcontroller Reference Manual, Rev. 2 12-26...
Page 514: External Bus Operations
Treated as 1-byte access. 12.4.2 External Bus Operations The following sections provide a functional description of the external bus, the bus cycles provided for data transfer operations, bus arbitration, and error conditions. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-27...
Page 515: External Clocking
On a read cycle, the master accepts the data bus contents as valid on the rising edge of the CLKOUT in which the TA signal is sampled asserted. See Figure 12-10 for an example of read timing. MPC5566 Microcontroller Reference Manual, Rev. 2 12-28 Freescale Semiconductor...
Page 516: Single-Beat Transfer
Asserts transfer start (TS) drives address and attributes Receives address Drives data CS access Asserts transfer acknowledge (TA) Asserts transfer acknowledge (TA) Receives data Figure 12-9. Basic Flow Diagram of a Single-Beat Read Cycle MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-29...
Page 517 Figure 12-10. Single-Beat 32-bit Read Cycle, CS Access, Zero Wait States CLKOUT ADDR[8:31] RD_WR TSIZ[0:1] BDIP DATA[0:31] Wait state DATA is valid Figure 12-11. Single-Beat 32-bit Read Cycle, CS Access, One Wait State MPC5566 Microcontroller Reference Manual, Rev. 2 12-30 Freescale Semiconductor...
Page 518 The EBI drives address and control signals an extra cycle because it uses a latched version of the external TA (1 cycle delayed) to terminate the cycle. Figure 12-12. Single-Beat 32-bit Read Cycle, Non-CS Access, Zero Wait States MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-31...
Page 519: Single-Beat Write Flow
Receives address Drives data Receives data CS access Asserts transfer acknowledge (TA) Asserts transfer acknowledge (TA) Waits 1 clock stops driving data Figure 12-13. Basic Flow Diagram of a Single-Beat Write Cycle MPC5566 Microcontroller Reference Manual, Rev. 2 12-32 Freescale Semiconductor...
Page 520 Figure 12-14. Single-Beat 32-bit Write Cycle, CS Access, Zero Wait States CLKOUT ADDR[8:31] RD_WR TSIZ[0:1] BDIP DATA is valid DATA[0:31] Wait state CS[n] WE[0:3] Figure 12-15. Single-Beat 32-bit Write Cycle, CS Access, One Wait State MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-33...
Page 521: Back-To-Back Accesses
See Section 12.4.2.9, “Termination Signals Protocol,” for more details. Figure 12-17, Figure 12-18, and Figure 12-19 show a few examples of back-to-back accesses on the external bus. MPC5566 Microcontroller Reference Manual, Rev. 2 12-34 Freescale Semiconductor...
Page 522 Figure 12-17. Back-to-Back 32-bit Reads to the Same CS Bank CLKOUT ADDR[8:31] RD_WR TSIZ[0:1] BDIP DATA[0:31] DATA is valid DATA is valid CS[n] CS[y] Figure 12-18. Back-to-Back 32-bit Reads to Different CS Banks MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-35...
Page 523 External Bus Interface (EBI) CLKOUT ADDR[8:31] RD_WR TSIZ[0:1] ’00’ BDIP DATA is valid DATA[0:31] DATA is valid Figure 12-19. Write-After-Read to the Same CS Bank MPC5566 Microcontroller Reference Manual, Rev. 2 12-36 Freescale Semiconductor...
Page 524 External Bus Interface (EBI) CLKOUT ADDR[8:31] RD_WR TSIZ[0:1] BDIP DATA is valid DATA is valid DATA[0:31] CS[n] Figure 12-20. Back-to-Back 32-bit Writes to the Same CS Bank MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-37...
Page 525: Burst Transfer
1. Except for the special case of a 32-bit non-chip select access in 16-bit data bus mode. See Section 12.4.2.11. MPC5566 Microcontroller Reference Manual, Rev. 2 12-38...
Page 526: Small Access Example #3: 32-Byte Read To 32-Bit Port With
Since burst writes are not supported by the EBI , the EBI negates BDIP during write cycles. 1. Except for the special case of a 32-bit non-chip select access in 16-bit data bus mode. See Section 12.4.2.11. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-39...
Page 527 Asserts transfer acknowledge (TA) Receives data Next-to-last data beat Negate BDIP Drives last data Asserts transfer acknowledge (TA) Receives last data Figure 12-22. Basic Flow Diagram of a Burst Read Cycle MPC5566 Microcontroller Reference Manual, Rev. 2 12-40 Freescale Semiconductor...
Page 528 Figure 12-23. Burst 32-bit Read Cycle, Zero Wait States CLKOUT ADDR[8:31] ADDR[29:31] = ‘000’ RD_WR TSIZ[0:1] ‘00’ Expects more data BDIP DATA[0:31] DATA is valid Wait state CS[n] Figure 12-24. Burst 32-bit Read Cycle, One Initial Wait State MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-41...
Page 529: Tbdip Effect On Burst Transfer
Expects more data BDIP DATA[0:31] DATA is valid Wait state Wait state Wait state Wait state CS[n] Figure 12-25. Burst 32-bit Read Cycle, One Wait State between Beats, TBDIP = 0 MPC5566 Microcontroller Reference Manual, Rev. 2 12-42 Freescale Semiconductor...
Page 530: Small Accesses (Small Port Size And Short Burst Length)
In external master mode, this means that the EBI keeps BB asserted and does not grant the bus to another master until the atomic transaction is complete. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-43...
Page 531 The following sections show a few examples of small accesses. The timing for the remaining cases in Table 12-17 can be extrapolated from these and the other timing diagrams in this document. MPC5566 Microcontroller Reference Manual, Rev. 2 12-44 Freescale Semiconductor...
Page 532: Small Access Example #1: 32-Bit Write To 16-Bit Port
64-bit boundary. In this case, an extra cycle is required between TA and the next TS to get the next 64-bits of write data internally and RD_WR negates during this extra cycle. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-45...
Page 533 Address + 0x10 (no carry) (after masking lower 4 bits) 0x000 0x10 0x10 0x008 0x18 0x10 0x010 0x00 0x00 0x018 0x08 0x00 0x020 0x30 0x30 0x028 0x38 0x30 0x030 0x20 0x20 0x038 0x28 0x20 MPC5566 Microcontroller Reference Manual, Rev. 2 12-46 Freescale Semiconductor...
Page 534: Size, Alignment, And Packaging On Transfers
Natural alignment for the EBI means: • Byte access can have any address • 16-bit access, address bit 31 must equal zero MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-47...
Page 535 The single byte of a byte-length operand is OP0, OP1, OP2, or OP3, depending on the address of the access. The convention can be seen in Figure 12-30. 32-bit 16-bit Byte Figure 12-30. Internal Operand Representation MPC5566 Microcontroller Reference Manual, Rev. 2 12-48 Freescale Semiconductor...
Page 536 Also applies when DBM = 1 for 16-bit data bus mode. This case consists of two 16-bit external transactions, the first fetching OP0 and OP1, the second fetching OP2 and OP3. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-49...
Page 537: Arbitration
This means that the EBI does not release the bus before the completion of the transactions which are considered as atomic. Figure 12-32 describes the basic protocol for bus arbitration. MPC5566 Microcontroller Reference Manual, Rev. 2 12-50 Freescale Semiconductor...
Page 538: External (Or Central) Bus Arbiter
BR 0 and BR 1 signals shown are inputs to the arbiter from the BR pin of each master. The BG 0 and BG 1 signals are outputs from the arbiter that connect to the BG pin of each master. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 539: Internal Bus Arbiter
EBI and the positive edge CLKOUT where BG is driven out asserted by the EBI. This is to prevent timing problems that can limit the operating frequency in external master mode. MPC5566 Microcontroller Reference Manual, Rev. 2 12-52 Freescale Semiconductor...
Page 540 ‘turns on’ ‘turns off’ ‘turns on’ (drives controls) (three-states controls) (drives controls) ATTR refers to control signals such as RD_WR and TSIZ. Figure 12-35. Internal/External Arbitration Timing Diagram (EARP = 1) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-53...
Page 541 0 or 1 MCU owner busy MCU owner busy 0 or 1 MCU owner busy MCU owner busy 0 or 1 MCU owner busy MCU owner busy 0 or 1 External bus wait MPC5566 Microcontroller Reference Manual, Rev. 2 12-54 Freescale Semiconductor...
Page 542 ‘window-of-opportunity’ is satisfied before the internal master be able to grab the bus again (depending on BR, BB, etc., according to normal transition logic). MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 543: Termination Signals Protocol
During idle periods on the external bus, the EBI drives TA negated as long as it is granted the bus; when it no longer owns the bus it lets go of TA. When an external MPC5566 Microcontroller Reference Manual, Rev. 2 12-56...
Page 544 TA cycle for the error to terminate correctly. External TEA assertion that occurs during the same cycle that TS is asserted by the EBI is always treated as an error (terminating the access) regardless of SCY. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-57...
Page 545 This is the earliest that the EBI can start another transfer, in the case of continuing a set of small accesses. For all other cases, an extra cycle is needed before the EBI can start another TS. Figure 12-37. Termination Signals Protocol Timing Diagram MPC5566 Microcontroller Reference Manual, Rev. 2 12-58 Freescale Semiconductor...
Page 546: Bus Operation In External Master Mode
To operate two masters in external master mode, one must be configured for internal arbitration and the other must be configured for external arbitration. Connecting three or more masters together in the same system is not supported by this EBI. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-59...
Page 547: Address Decoding For External Master Accesses
EBI responds with a bus error. 1. Except for the special case of a 32-bit non-chip select access in 16-bit data bus mode. See Section 12.4.2.11, “Non-Chip-Select Burst in 16-bit Data Bus Mode”. MPC5566 Microcontroller Reference Manual, Rev. 2 12-60 Freescale Semiconductor...
Page 548: Bus Transfers Initiated By An External Master
MCU asserts TA, and the external master can proceed with another external master access, or relinquish the bus. If an address or data error was detected internally, the MCU asserts TEA for one clock. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-61...
Page 549 External arbiter is the EBI unless a central arbiter device is used. Determined by the internal arbiter of the external master device. Figure 12-39. Basic Flow Diagram of an External Master Read Access MPC5566 Microcontroller Reference Manual, Rev. 2 12-62 Freescale Semiconductor...
Page 550 External arbiter is the EBI unless a central arbiter device is used. Determined by the internal arbiter of the external master device. Figure 12-40. Basic Flow Diagram of an External Master Write Cycle MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-63...
Page 551 If the external master is another MCU with this EBI, then BB and other control pins are turned off as shown due to use of latched TA internally. This extra cycle is not required by the slave EBI. Figure 12-41. External Master Read from MCU MPC5566 Microcontroller Reference Manual, Rev. 2 12-64 Freescale Semiconductor...
Page 552 If the external master is another MCU with this EBI, then DATA remains valid as shown due to use of latched TA internally. These extra data valid cycles (past TA) are not required by the slave EBI. Figure 12-42. External Master Write to MCU MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-65...
Page 553: Bus Transfers Initiated By The Ebi In External Master Mode
3. Drives address and attributes Receives address Drives data CS access Asserts transfer acknowledge (TA) Asserts transfer acknowledge (TA) Receives data Figure 12-43. Basic Flow Diagram of an EBI Read Access in External Master Mode MPC5566 Microcontroller Reference Manual, Rev. 2 12-66 Freescale Semiconductor...
Page 554: Back-To-Back Transfers In External Master Mode
This case assumes the MCU has no higher priority internal request pending and is able to park the external master on the bus. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-67...
Page 555 External master starts read access Both masters off ADDR[8:31] RD_WR TSIZ[0:1] BDIP DATA[0:31] DATA is valid DATA is valid CS[n] Figure 12-45. External Master Read followed by MCU Read to Same CS Bank MPC5566 Microcontroller Reference Manual, Rev. 2 12-68 Freescale Semiconductor...
Page 556 External master starts read access Both masters off ADDR[8:31] RD_WR TSIZ[0:1] BDIP DATA[0:31] DATA is valid DATA is valid CS[n] CS[y] Figure 12-46. MCU Read followed by External Master Read to Different CS Bank MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-69...
Page 557: Non-Chip-Select Burst In 16-Bit Data Bus Mode
For this case, a special two-beat burst protocol is used for reads and writes, so that the EBI-slave can internally generate one 32-bit read or write access (thus 32-bit coherent), as opposed to two separate 16-bit accesses. MPC5566 Microcontroller Reference Manual, Rev. 2 12-70 Freescale Semiconductor...
Page 558 RD_WR ‘00’ TSIZ[0:1] BDIP TS (Input) DATA[0:15] TA (Output) DATA is valid Minimum DATA is valid two wait states Figure 12-48. External Master 32-bit Read from MCU with DBM = 1 MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-71...
Page 559: Calibration Bus Operation
12-18, except the CS[y] is replaced by CAL_CS[y]. Timing for other cases on the calibration bus can similarly be derived from other figures in this document (by replacing CS with CAL_CS). MPC5566 Microcontroller Reference Manual, Rev. 2 12-72 Freescale Semiconductor...
Page 560: Initialization And Application Information
This includes flash and external SRAM memories with a compatible burst interface. BDIP is required only for some SDR memories. Figure 12-48 shows a block diagram of an MCU connected to a 32-bit SDR burst memory. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-73...
Page 561: Running With Asynchronous Memories
Because actual input setup (10.8 ns) is greater than the input setup specification (4.0 ns), three wait states is sufficient. If the input setup is less than 4.0 ns, use four wait states. MPC5566 Microcontroller Reference Manual, Rev. 2 12-74...
Page 562: Timing And Connections For Asynchronous Memories
16-bit asynchronous memory using three wait states. CLKOUT ADDR[8:31] WE[0:1] DATA[0:31] 3 wait states DATA is valid Figure 12-53. Read Operation to Asynchronous Memory, Three Initial Wait States MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-75...
Page 563 16-bit asynchronous memory using three wait states. CLKOUT CS[n] ADDR[8:31] WE[0:1] DATA is valid DATA[0:31] three wait states Figure 12-54. Write Operation to Asynchronous Memory, Three Initial Wait States MPC5566 Microcontroller Reference Manual, Rev. 2 12-76 Freescale Semiconductor...
Page 564: Connecting An Mcu To Multiple Memories
• Changes in bit fields: — Removed these variable timing attributes from option register: CSNT, ACS, TRLX, EHTR — Removed LBDIP base register bit, now late BDIP assertion is default behavior MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 12-77...
Page 565 Calibration features implemented by four calibration chip selects • Removed support for three-master systems • Address decoding for external master accesses uses 4-bit code to determine internal slave instead of straight address decode MPC5566 Microcontroller Reference Manual, Rev. 2 12-78 Freescale Semiconductor...
Page 566: Introduction
Flash BIU contains a two-entry prefetch buffer, each entry containing 256 bits of data, and an associated controller that prefetches sequential lines of data from the flash array into the buffer. Prefetch MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 567 Flash Array Blocks Low address space —256 KB Low address space Mid address space —256 KB Mid address space High address space — 2.5 MB High address space Figure 13-2. Flash Array Diagram MPC5566 Microcontroller Reference Manual, Rev. 2 13-2 Freescale Semiconductor...
Page 568: Features
Section 13.4.2, “Flash Memory Array: User Mode.” 13.1.4.2 Stop Mode In stop mode (FLASH_MCR[STOP] = 1), all DC current sources in the flash are disabled. Refer to Section 13.4.3, “Flash Memory Array: Stop Mode.” MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 13-3...
Page 569: External Signal Description
The access time of the internal flash is lengthened based on the address range being accessed. To access an area with a slower access time, the address is modified per Table 13-3. MPC5566 Microcontroller Reference Manual, Rev. 2 13-4 Freescale Semiconductor...
Page 570 01101 0x1600_0000 0x162F_FFFF 10101 0x1700_0000 0x172F_FFFF 11101 0x1800_0000 0x182F_FFFF 00110 0x1900_0000 0x192F_FFFF 01110 0x1A00_0000 0x1A2F_FFFF 10110 0x1B00_0000 0x1B2F_FFFF 11110 0x1C00_0000 0x1C2F_FFFF 00111 0x1D00_0000 0x1D2F_FFFF 01111 0x1E00_0000 0x1E2F_FFFF 10111 0x1F00_0000 0x1F2F_FFFF 11111 MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 13-5...
Page 571: Flash Memory Map
User Array base + (0x0000_0000–0x0003_FFFF) Low address space (256 KB) User Array base + (0x0004_0000–0x0007_FFFF) Mid address space (256 KB) User Array base + (0x0008_0000–0x2F00_FFFF) High address space (2.5 MB) User MPC5566 Microcontroller Reference Manual, Rev. 2 13-6 Freescale Semiconductor...
Page 572 128 KB Array base + 0x0026_0000 128 KB Array base + 0x0028_0000 128 KB Array base + 0x002A_0000 128 KB Array base + 0x002C_0000 128 KB Array base + 0x002E_0000 128 KB MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 13-7...
Page 573 Address register Register base + 0x001C FLASH_BIUCR Flash bus interface unit control register Register base + 0x0020 FLASH_BIUAPR Flash bus interface unit access protection register Register base + — Reserved — (0x0030–0x7FFF) MPC5566 Microcontroller Reference Manual, Rev. 2 13-8 Freescale Semiconductor...
Page 574: Register Descriptions
110 The LAS value of 110 provides two 16-KB blocks, two 48-KB blocks, and two 64-KB blocks. 12–14 Reserved. Mid address space size. Corresponds to the configuration of the mid address space. MAS is read only. 0 Two 128-KB blocks are available MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 13-9...
Page 575 In STOP mode all address spaces, registers, and register bits are deactivated except for the FLASH_MCR[STOP] bit. 0 Flash is not in stop mode; the read state is active. 1 Flash is in stop mode. MPC5566 Microcontroller Reference Manual, Rev. 2 13-10 Freescale Semiconductor...
Page 576 The flash module cannot exit erase suspend and clear DONE while EHV is low. ESUS is cleared on reset. 0 Erase sequence is not suspended. 1 Erase sequence is suspended. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 13-11...
Page 577: Mcr Simultaneous Register Writes
(FLASH_MCR).” The write locks detailed in that section do not consider the effects of trying to write two or more bits simultaneously. The effects of writing bits simultaneously that put the flash module in an illegal state are detailed here. MPC5566 Microcontroller Reference Manual, Rev. 2 13-12 Freescale Semiconductor...
Page 578: Low/Mid Address Space Block Locking Register (Flash_Lmlr)
The reset value of these bits is determined by flash values in the shadow row. Erasing the array sets the reset value to 1. Figure 13-6. Low/Mid Address Space Block Locking Register (FLASH_LMLR) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 579 LLOCK bits are used, if a configuration has six 16-KB blocks in the low address space, the block residing at address array base + 0, corresponds to LLOCK0. The next 16-KB block corresponds to LLOCK1, and so on up to LLOCK5. MPC5566 Microcontroller Reference Manual, Rev. 2 13-14 Freescale Semiconductor...
Page 580: High Address Space Block Locking Register (Flash_Hlr)
LMLOCK field (FLASH_LMLR), determine if the block is locked from program or erase. An “OR” of FLASH_LMLR and FLASH_SLMLR determine the final lock status. Refer to Section 13.3.2.2, “Low/Mid Address Space Block Locking Register (FLASH_LMLR)” for more information on FLASH_LMLR. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 13-15...
Page 581 (FLASH_LMLR). SLLOCK is not writable unless SLE is high. In the event that blocks are not present (due to configuration or total memory size), the SLLOCK bits default to locked, and are not writable. MPC5566 Microcontroller Reference Manual, Rev. 2 13-16 Freescale Semiconductor...
Page 582: Low/Mid Address Space Block Select Register (Flash_Lmsr)
Three low address space blocks are selected for erase 0b1111 Four low address space blocks are selected for erase 0b0001_1111 Five low address space blocks are selected for erase 0b0011_1111 Six low address space blocks are selected for erase MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 13-17...
Page 583: High Address Space Block Select Register (Flash_Hsr)
RWW operation, where the read senses an ECC error and the state machine fails simultaneously. This address is always a doubleword address that selects 64 bits. In normal operating mode, the FLASH_AR is not writable. MPC5566 Microcontroller Reference Manual, Rev. 2 13-18 Freescale Semiconductor...
Page 584: Flash Bus Interface Unit Control Register (Flash_Biucr)
Only use a 32-bit write operation to write to this register. Address: Base (0xC3F8_8000) + 0x001C Access: R/W Reset WWSC RWSC DPFEN IPFEN PFLIM BFEN Reset Figure 13-12. Flash Bus Interface Unit Control Register (FLASH_BIUCR) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 13-19...
Page 585 00 No prefetching is triggered by an instruction read access 01 Prefetching can be triggered only by an instruction burst read access 10 Reserved 11 Prefetching can be triggered by any instruction read access MPC5566 Microcontroller Reference Manual, Rev. 2 13-20 Freescale Semiconductor...
Page 586 For maximum flash performance, set to 0b1. This setting allows for 100 MHz system clock with 2% frequency modulation. This setting allows for 130 MHz system clock with 2% frequency modulation. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 13-21...
Page 587: Flash Bus Interface Unit Access Protection Register (Flash_Biuapr)
Several prefetch control algorithms are available for controlling line read buffer fills. Prefetch triggering can be restricted to instruction accesses only, data accesses only, or can be unrestricted. Prefetch triggering can also be controlled on a per-master basis. MPC5566 Microcontroller Reference Manual, Rev. 2 13-22 Freescale Semiconductor...
Page 588: Fbiu Basic Interface Protocol
When an error response is received, the Flash BIU marks a line read buffer as invalid. An error response can be signaled on read or write operations. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 13-23...
Page 589: Fbiu Line Read Buffers And Prefetch Operation
Prefetch triggering can be enabled for data reads. Triggering can be enabled for all data reads or only for data burst reads. Prefetches are not triggered by write cycles. MPC5566 Microcontroller Reference Manual, Rev. 2 13-24...
Page 590: Fbiu Per-Master Prefetch Triggering
The read state is active when FLASH_MCR[PGM] = 1 and/or FLASH_MCR[ERS] = 1 and high voltage operation is ongoing (read while write). NOTE Reads done to the partitions being operated on (either erased or programmed) result in an errors and the FLASH_MCR[RWE] bit is set. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 13-25...
Page 591: Read While Write (Rww)
0 to a logic 1. Addresses in locked/disabled blocks cannot be programmed. The user can program the values in any or all of eight words within a page in a single program sequence. Word addresses are selected using bits 4:2 of the page-bound word. MPC5566 Microcontroller Reference Manual, Rev. 2 13-26 Freescale Semiconductor...
Page 592 An interlock write must be performed before setting FLASH_MCR[EHV]. The user can terminate a program sequence by clearing FLASH_MCR[PGM] prior to setting FLASH_MCR[EHV]. If multiple writes are done to the same location the data for the last write is used in programming. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 13-27...
Page 593 The user cannot abort a program sequence while in program suspend. WARNING Aborting a program operation leaves the flash core addresses being programmed in an indeterminate data state. This can be recovered by executing an erase on the affected blocks. MPC5566 Microcontroller Reference Manual, Rev. 2 13-28 Freescale Semiconductor...
Page 594 Note: PEG remains valid under this condition until EHV is set high or PGM is cleared. Step 9 Write MCR PGM = 0 ESUS User mode read state Erase suspend Figure 13-14. Program Sequence MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 13-29...
Page 595: Software Locking
FLASH_LMSR or FLASH_HSR. If the shadow row is to be erased, this step can be skipped, and FLASH_LMSR and FLASH_HSR are ignored. For shadow row erase, refer to section Section 13.4.2.5, “Flash Shadow Block” for more information. MPC5566 Microcontroller Reference Manual, Rev. 2 13-30 Freescale Semiconductor...
Page 596: Flash Erase Suspend/Resume
During suspend, all reads to flash core locations targeted for program and blocks targeted for erase return indeterminate data. Programming locations in blocks targeted for erase during erase-suspended program can result in corrupted data. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 13-31...
Page 597 This can extend the time required for the erase operation. WARNING In an erase-suspended program, programming flash locations in blocks which were being operated on in the erase can corrupt flash core data. MPC5566 Microcontroller Reference Manual, Rev. 2 13-32 Freescale Semiconductor...
Page 598 Note: PEG remains valid under this condition until EHV is set high or ERS is cleared. Step 9 Write MCR ERS = 0 User mode read state Figure 13-15. Erase Sequence MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 13-33...
Page 599: Flash Shadow Block
The flash module latches the value of the control word prior to the negation of system reset. Censorship logic uses the value latched in the flash module to disable access to internal flash, disable the NDI, prevent modification of the FLASH_BIUAPR bitfields, and/or set the boot default value. MPC5566 Microcontroller Reference Manual, Rev. 2 13-34 Freescale Semiconductor...
Page 600: Flash Disable
The Nexus port controller is held in reset when in censored mode. The FBIU returns a bus error if an access is attempted while flash access is disabled. Flash access is any read, write or execute access. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 13-35...
Page 601: Flash_Biuapr Modification
FLASH_MCR[PGM] = 1 or FLASH_MCR[ERS] = 1. In stop mode all DC current sources in the flash module are disabled. Stop mode is exited by clearing the FLASH_MCR[STOP] bit. MPC5566 Microcontroller Reference Manual, Rev. 2 13-36 Freescale Semiconductor...
Page 602: Flash Memory Array: Reset
After reset is negated, register accesses can be performed, although registers that require updating from shadow information, or other inputs, cannot read updated values until flash exits reset. FLASH_MCR[DONE] can be polled to determine if reset has been exited. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 13-37...
Page 603 Flash Memory MPC5566 Microcontroller Reference Manual, Rev. 2 13-38 Freescale Semiconductor...
Page 604: Introduction
External Signal Description The external signal for SRAM is the V RAM power supply. If the standby feature of the SRAM is STBY not used, tie the V pin to V STBY MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 14-1...
Page 605: Register Memory Map
1. The ECC mechanism checks the entire 64-bit data bus for errors, detecting and either correcting or flagging errors. 2. The write data bytes (1-, 2-, or 4-byte segment) are merged with the corrected 64 bits on the data bus. MPC5566 Microcontroller Reference Manual, Rev. 2 14-2 Freescale Semiconductor...
Page 606: Access Timing
Pipelined read Read Idle Pipelined read 1,0,0,0 Burst read 64-bit write 2,0,0,0 Burst read 0,0,0,0 (read from the same address) 8-, 16-, or 32-bit write 1,0,0,0 (read from a different address) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 14-3...
Page 607: Reset Effects On Sram Accesses
If the write is not the entire 64-bits (8-, 16-, or 32-bits), a read / modify / write operation is generated that checks the ECC value upon the read. Refer to Section 14.6, “SRAM ECC Mechanism.” NOTE You must initialize SRAM, even if the application does not use ECC reporting. MPC5566 Microcontroller Reference Manual, Rev. 2 14-4 Freescale Semiconductor...
Page 608: Example Code
# write all 32 GPRs to SRAM addi r11,r11,128 # inc the ram ptr; 32 GPRs * 4 bytes = 128 bdnz init_ram_loop # loop for 128k of SRAM # done MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 14-5...
Page 609 SRAM MPC5566 Microcontroller Reference Manual, Rev. 2 14-6 Freescale Semiconductor...
Page 610: Introduction
Figure 15-1 shows the block diagram of the FEC. The FEC is implemented with a combination of hardware and microcode. The off-chip (Ethernet) interfaces are compliant with industry and IEEE® 802.3 standards. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-1...
Page 611 RAM I/F controller FEC Bus Transmit Receive counters MDEN FEC_TX_EN FEC_TX_CLK FEC_RX_CLK FEC_TXD[3:0] FEC_RX_DV FEC_CRS FEC_TX_ER FEC_RXD[3:0] FEC_COL FEC_RX_ER MII or 7-WIRE DATA FEC_MDIO FEC_MDC OPTION Figure 15-1. FEC Block Diagram MPC5566 Microcontroller Reference Manual, Rev. 2 15-2 Freescale Semiconductor...
Page 612: Overview
FEC but provides valuable counters for network management. The counters supported are the RMON (RFC 1757) Ethernet Statistics group and some of the IEEE® 802.3 counters. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-3...
Page 613: Features
TCR[FDEN] bit. When configured for full duplex mode, flow control can be enabled. See the TCR[RFC_PAUSE] and TCR[TFC_PAUSE] bits, the RCR[FCE] bit, and Section 15.4.10, “Full Duplex Flow Control,” for more details. MPC5566 Microcontroller Reference Manual, Rev. 2 15-4 Freescale Semiconductor...
Page 614: Interface Options
The FEC is programmed by a combination of control/status registers (CSRs) and buffer descriptors. The CSRs are used for mode control and to extract global status information. The descriptors are used to pass data buffers and related buffer information between the hardware and software. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-5...
Page 615: Top Level Module Memory Map
5 of ANSI/IEEE® Std. 802.3 (1998 edition). The IEEE® Basic Package objects are supported by the FEC but do not require counters in the MIB block. In addition, some of the MPC5566 Microcontroller Reference Manual, Rev. 2 15-6...
Page 616 0x0268 IEEE_T_CSERR Frames transmitted with carrier sense error 0x026C IEEE_T_SQE Frames transmitted with SQE error 0x0270 IEEE_T_FDXFC Flow control pause frames transmitted 0x0274 IEEE_T_OCTETS_OK Octet count for frames transmitted without error MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-7...
Page 617 0x02E0 IEEE_R_OCTETS_OK Octet count for frames received without error All accesses to and from the FEC memory map must be 32-bit accesses. There is no support for accesses other than 32-bit. MPC5566 Microcontroller Reference Manual, Rev. 2 15-8 Freescale Semiconductor...
Page 618: Registers
Global read burst enable from XBAR slave port designated by FXSBEn 0 = Read bursting from all XBAR slave ports is disabled. 1 = Read bursting is enabled from any XBAR slave port whose FXSBEn bit is asserted. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-9...
Page 619 In other words, an error response to the first half is seen in the response to the second half, even if the second half does not error. 11–31 — Reserved, must be cleared. MPC5566 Microcontroller Reference Manual, Rev. 2 15-10 Freescale Semiconductor...
Page 620: Fec Registers
Figure 15-3. Ethernet Interrupt Event Register (EIR) “w1c” signifies the bit is cleared by writing 1 to it. Table 15-4 describes the fields and functions of the Ethernet interrupt event register: MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-11...
Page 621: Ethernet Interrupt Mask Register (Eimr)
EIR and EIMR registers are set, the interrupt is signaled to the CPU. The interrupt signal remains asserted until a 1 is written to the EIR bit (write 1 to clear) or a 0 is written to the EIMR bit. MPC5566 Microcontroller Reference Manual, Rev. 2 15-12 Freescale Semiconductor...
Page 622: Receive Descriptor Active Register (Rdar)
0, the FEC clears R_DES_ACTIVE and stops receive descriptor ring polling until the bit is set again, signifying that additional descriptors were placed into the receive descriptor ring. The RDAR register is cleared at reset and when ECR[ETHER_EN] is cleared. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-13...
Page 623: Transmit Descriptor Active Register (Tdar)
The TDAR register is cleared at reset, when ECR[ETHER_EN] is cleared, or when ECR[RESET] is set. Address: Base + 0x0014 Access: User R/W X_DES_ ACTIVE Reset Reset Figure 15-6. Transmit Descriptor Active Register (TDAR) MPC5566 Microcontroller Reference Manual, Rev. 2 15-14 Freescale Semiconductor...
Page 624: Ethernet Control Register (Ecr)
This bit is automatically cleared by hardware during the reset sequence. The reset sequence takes approximately 8 system clock cycles after RESET is written with a 1. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-15...
Page 625: Mii Management Frame Register (Mmfr)
To generate an IEEE® 802.3-compliant MII management interface write frame (write to a PHY register), the application must write {01 01 PHYAD REGAD 10 DATA} to the MMFR register. Writing this pattern MPC5566 Microcontroller Reference Manual, Rev. 2 15-16 Freescale Semiconductor...
Page 626: Mii Speed Control Register (Mscr)
Asserting this bit causes preamble (32 1’s) not to be prepended to the MII management frame. The MII DIS_PREAMBLE standard allows the preamble to be dropped if the attached PHY devices does not require it. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-17...
Page 627: Mib Control Register (Mibc)
MIB counters in RAM the application must disable the MIB block, then clear all the MIB RAM locations, then enable the MIB block. The MIB_DISABLE bit is reset to 1. See Table 15-2 for the locations of the MIB counters. MPC5566 Microcontroller Reference Manual, Rev. 2 15-18 Freescale Semiconductor...
Page 628: Receive Control Register (Rcr)
ECR[ETHER_EN] = 0 (initialization time). Address: Base + 0x0084 Access: User R/W MAX_FL Reset MII_ PROM DRT LOOP MODE Reset Figure 15-11. Receive Control Register (RCR) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-19...
Page 629 Internal loopback. If set, transmitted frames are looped back internal to the device and LOOP LOOP the transmit output signals are not asserted. The system clock is substituted for the FEC_TX_CLK when LOOP is asserted. DRT must be set to zero when asserting LOOP. MPC5566 Microcontroller Reference Manual, Rev. 2 15-20 Freescale Semiconductor...
Page 630: Transmit Control Register (Tcr)
The frame is transmitted again once GTS is cleared. Previous frames can reside in the transmit FIFO that are transmitted when GTS is reasserted. To avoid this condition, deassert ECR[ETHER_EN] following the GRA interrupt. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-21...
Page 631: Physical Address Low Register (Palr)
Bytes 0 (bits 0:7), 1 (bits 8:15), 2 (bits 16:23) and 3 (bits 24:31) of the 6-byte individual address to PADDR1 be used for exact match, and the Source Address field in PAUSE frames. MPC5566 Microcontroller Reference Manual, Rev. 2 15-22 Freescale Semiconductor...
Page 632: Physical Address Upper Register (Paur)
This register is not reset and must be initialized by the application. Section 15.4.10, “Full Duplex Flow Control” for information on using the OPD register. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-23...
Page 633: Descriptor Individual Upper Address Register (Iaur)
DA field of receive frames with an individual DA. This register is not reset and must be initialized by the application. MPC5566 Microcontroller Reference Manual, Rev. 2 15-24 Freescale Semiconductor...
Page 634: Descriptor Individual Lower Address (Ialr)
Address: Base + 0x011C Access: User R/W IADDR2 Reset IADDR2 Reset “U” signifies a bit that is uninitialized. See the Preface of the book. Figure 15-19. Descriptor Individual Lower Address Register (IALR) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-25...
Page 635: Descriptor Group Upper Address (Gaur)
The GALR register is written by the application. This register contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. This register must be initialized by the application. MPC5566 Microcontroller Reference Manual, Rev. 2 15-26 Freescale Semiconductor...
Page 636: Fifo Transmit Fifo Watermark Register (Tfwr)
FIFO underrun due to contention for the system bus. The byte counts of the TFWR field can require modification to match a given system requirement. Address: Base + 0x0144 Access: User R/W Reset X_WMRK Reset Figure 15-22. FIFO Transmit FIFO Watermark Register (TFWR) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-27...
Page 637: Fifo Receive Bound Register (Frbr)
FRSR. The receive FIFO uses addresses from FRSR to FRBR inclusive. The FRSR register is initialized by hardware at reset. FRSR only needs to be written to change the default value. MPC5566 Microcontroller Reference Manual, Rev. 2 15-28 Freescale Semiconductor...
Page 638: Receive Descriptor Ring Start (Erdsr)
This register is not reset and must be initialized by the application prior to operation. Address Base + 0x0180 Access: R/W R_DES_START Reset R_DES_START Reset “U” signifies a bit that is uninitialized. Figure 15-25. Receive Descriptor Ring Start Register (ERDSR) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-29...
Page 639: Transmit Buffer Descriptor Ring Start (Etdsr)
To allow one maximum size frame per buffer, EMRBR must be set to RCR[MAX_FL] or larger. The EMRBR must be evenly divisible by 16. To insure this, bits 28-31 are MPC5566 Microcontroller Reference Manual, Rev. 2 15-30...
Page 640: Initialization Sequence
FEC. 15.4.1.1 Hardware Controlled Initialization In the FEC, registers and control logic that generate interrupts are reset by hardware. A hardware reset deasserts output signals and resets general configuration bits. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-31...
Page 641: Application Initialization (Prior To Asserting Ecr[Ether_En])
Clear MIB_RAM (locations Base + 0x0200–0x02FC) FEC FIFO/DMA registers that require initialization are defined in Table 15-30. Table 15-30. FEC Application Initialization (Before ECR[ETHER_EN]) Description Initialize FRSR (optional) Initialize EMRBR Initialize ERDSR MPC5566 Microcontroller Reference Manual, Rev. 2 15-32 Freescale Semiconductor...
Page 642: Microcontroller Initialization
(RCR[MII_MODE] = 1), there are 18 signals defined by the IEEE® 802.3 standard and supported by the EMAC. These signals are shown in Table 15-32 below. Table 15-32. MII Mode Signal Description EMAC Signal Transmit Clock FEC_TX_CLK Transmit Enable FEC_TX_EN Transmit Data FEC_TXD[3:0] MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-33...
Page 643: Fec Frame Transmission
60 bit times. If so, the transmission begins after waiting an additional 36 bit times (96 bit times after carrier sense originally became inactive). See Section 15.4.14.1, “Transmission Errors” for more details. MPC5566 Microcontroller Reference Manual, Rev. 2 15-34 Freescale Semiconductor...
Page 644: Fec Frame Reception
00 bit sequence is detected prior to the SFD byte, the frame is ignored. After the first 6 bytes of the frame have been received, the FEC performs address recognition on the frame. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 645: Ethernet Address Recognition
If the DA is the individual (unicast) address, the microcontroller performs an individual exact match comparison between the DA and 48-bit physical address that the application programs in the PALR and MPC5566 Microcontroller Reference Manual, Rev. 2 15-36 Freescale Semiconductor...
Page 646 NOTES: BC_REJ - field in RCR register (BroadCast REJect) PROM - field in RCR register (PROMiscous mode) Pause Frame - valid Pause frame received Figure 15-28. Ethernet Address Recognition—Receive Block Decisions MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-37...
Page 647: Hash Algorithm
Those that do reach memory must be further filtered by the processor to determine if they truly contain one of the eight desired addresses. The effectiveness of the hash table declines as the number of addresses increases. MPC5566 Microcontroller Reference Manual, Rev. 2 15-38 Freescale Semiconductor...
Page 648 F5:ff:ff:ff:ff:ff DB:ff:ff:ff:ff:ff FB:ff:ff:ff:ff:ff BB:ff:ff:ff:ff:ff 8B:ff:ff:ff:ff:ff 0B:ff:ff:ff:ff:ff 3B:ff:ff:ff:ff:ff 7B:ff:ff:ff:ff:ff 5B:ff:ff:ff:ff:ff 27:ff:ff:ff:ff:ff 0x10 07:ff:ff:ff:ff:ff 0x11 57:ff:ff:ff:ff:ff 0x12 77:ff:ff:ff:ff:ff 0x13 F7:ff:ff:ff:ff:ff 0x14 C7:ff:ff:ff:ff:ff 0x15 97:ff:ff:ff:ff:ff 0x16 A7:ff:ff:ff:ff:ff 0x17 99:ff:ff:ff:ff:ff 0x18 B9:ff:ff:ff:ff:ff 0x19 F9:ff:ff:ff:ff:ff 0x1A MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-39...
Page 649 0x2B BF:ff:ff:ff:ff:ff 0x2C 9F:ff:ff:ff:ff:ff 0x2D DF:ff:ff:ff:ff:ff 0x2E EF:ff:ff:ff:ff:ff 0x2F 93:ff:ff:ff:ff:ff 0x30 B3:ff:ff:ff:ff:ff 0x31 F3:ff:ff:ff:ff:ff 0x32 D3:ff:ff:ff:ff:ff 0x33 53:ff:ff:ff:ff:ff 0x34 73:ff:ff:ff:ff:ff 0x35 23:ff:ff:ff:ff:ff 0x36 13:ff:ff:ff:ff:ff 0x37 3D:ff:ff:ff:ff:ff 0x38 0D:ff:ff:ff:ff:ff 0x39 5D:ff:ff:ff:ff:ff 0x3A MPC5566 Microcontroller Reference Manual, Rev. 2 15-40 Freescale Semiconductor...
Page 650: Full Duplex Flow Control
TCR[GTS] internally. When the transmission of data frames stops, the EIR[GRA] (graceful stop complete) interrupt asserts. Following EIR[GRA] assertion, the pause frame is transmitted. On completion of pause frame transmission, flow control pause (TCR[TFC_PAUSE]) and TCR[GTS] are deasserted internally. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-41...
Page 651: Inter-Packet Gap (Ipg) Time
FIFO underrun and receive FIFO overflow. For external loopback set RCR[LOOP] = 0, RCR[DRT] = 0 and configure the external transceiver for loopback. MPC5566 Microcontroller Reference Manual, Rev. 2 15-42 Freescale Semiconductor...
Page 652: Ethernet Error-Handling Procedure
When this error occurs, the FEC closes the buffer, sets the HB bit in the EIR register, and generates the HBERR interrupt if it is enabled. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 653: Reception Errors
FEC that a buffer has been placed in external memory for the transmit or receive data traffic, respectively. The hardware reads the BDs and “consumes” the buffers after they have been produced. After MPC5566 Microcontroller Reference Manual, Rev. 2 15-44...
Page 654: Driver/Dma Operation With Transmit Bds
Unlike transmit, the length of the receive frame is unknown by the driver ahead of time. Therefore the driver must set a variable to define the length of all receive buffers. In the FEC, this variable is written to the EMRBR register. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-45...
Page 655: Ethernet Receive Buffer Descriptor (Rxbd)
Offset + 2 Data Length Offset + 4 Rx Data Buffer Pointer - A [0:15] Offset + 6 Rx Data Buffer Pointer - A [16:31] Figure 15-30. Receive Buffer Descriptor (RxBD) MPC5566 Microcontroller Reference Manual, Rev. 2 15-46 Freescale Semiconductor...
Page 656 This bit is valid only if the L-bit is set. If this bit is set the CR bit is not set. Offset + 0 Bit 12 — Reserved. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-47...
Page 657: Ethernet Transmit Buffer Descriptor (Txbd)
Transmit frame status is indicated via individual interrupt bits (error conditions) and in statistic counters in the MIB block. See Section 15.3.3, “MIB Block Counters Memory Map” for more details. MPC5566 Microcontroller Reference Manual, Rev. 2 15-48 Freescale Semiconductor...
Page 658 (only valid if L = 1). 0 No effect 1 Transmit the CRC sequence inverted after the last data byte (regardless of TC value). Offset + 0 Bits [7:15] — Reserved. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 15-49...
Page 659 R bit in the first BD for the frame. The driver must follow that with a write to TDAR which triggers the FEC to poll the next BD in the ring. MPC5566 Microcontroller Reference Manual, Rev. 2 15-50 Freescale Semiconductor...
Page 660: Introduction
MCU resources to start application code execution. Figure 16-1 is a block diagram of the BAM. Peripheral bridge B control block Figure 16-1. BAM Block Diagram MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 16-1...
Page 661: Features
Use external boot mode when the boot code and configuration information are located in external memory that is connected to the EBI. Enable bus arbitration for multiprocessor systems to allow a boot option. Do not select external boot mode for devices without an external bus. MPC5566 Microcontroller Reference Manual, Rev. 2 16-2 Freescale Semiconductor...
Page 662: Serial Boot Mode
• Address and contents of the reset configuration halfword (RCHW), which contains the address and configuration options for the boot code. Refer to Chapter 4, “Reset,” for information about the RCHW. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 16-3...
Page 663: Bam Program Operation
BOOTCFG[0:1] located in the reset status register (SIU_RSR) • Censorship control field located at 0x00FF_FDE0 in the shadow row of internal flash • Serial boot control field located at 0x00FF_FDE2 in the shadow row of internal flash MPC5566 Microcontroller Reference Manual, Rev. 2 16-4 Freescale Semiconductor...
Page 664 Nexus interface. The censorship word is programmed at the factory to contain 0x55AA_55AA, which uses a password in internal flash to activate serial boot mode for an uncensored (public) device. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 16-5...
Page 665 Flash password (64-bit value in the shadow row of internal flash at address 0x00FF_FDD8). Serial boot flash password starts at address 0x00FF_FDD8: Address: 0x00FF_FDD8 Value: 0xFEED Binary value Hex value Address: 0x00FF_FDDA Value: 0xFACE Binary value Hex value MPC5566 Microcontroller Reference Manual, Rev. 2 16-6 Freescale Semiconductor...
Page 666: Internal Boot Mode
Address 0x0000_0000 0x0000_4000 0x0001_0000 0x0001_C000 0x0002_0000 0x0003_0000 If the BAM fails to find a valid RCHW, it assumes the flash is erased or corrupt and switches to serial boot operating mode. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 16-7...
Page 667: External Boot Modes
• Cache enabled 0x2000_0000 0x2000_0000 16 MB • Not guarded • Big endian • Global PID This allows code written to run from internal flash memory to execute from external memory. MPC5566 Microcontroller Reference Manual, Rev. 2 16-8 Freescale Semiconductor...
Page 668: Single Bus Master Or Multiple Bus Masters
To use external boot mode with external arbitration, the BAM program must also configure the following bits in addition to the bits set for External Boot with no Arbitration mode: MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 16-9...
Page 669 The BAM does not write to the PCR for this signal; the value is the PCR default value. Refer to Chapter 6, “System Integration Unit (SIU)” for the signal PCR default values. MPC5566 Microcontroller Reference Manual, Rev. 2 16-10 Freescale Semiconductor...
Page 670: Read The Reset Configuration Halfword
RCHW was found, then the MMU is configured the same way as for internal boot mode. The EBI is disabled and all bus pins function as GPIO. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 671: Serial Boot Mode Flexcan And Esci Configuration
The BAM ignores the following errors: • Bit 1 errors • Bit 0 errors • Acknowledge errors • Cyclic redundancy code errors • Form errors • Stuffing errors • TX error counter errors MPC5566 Microcontroller Reference Manual, Rev. 2 16-12 Freescale Semiconductor...
Page 672 Watchdog Timeout SCI Baud Rate (MHz) Frequency (MHz) Baud Rate Period (seconds) ÷ 1250 ÷ 60 ) ÷ f = 1.5 x f (2.5 x 2 ref_crystal ref_crystal 9600 200 K 28.0 MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 16-13...
Page 673: Download Process For Flexcan Serial Boot Mode
1. Download the 64-bit password. 2. Download the start address, VLE flag, and the number of data bytes to download. 3. Download the data. 4. Execute the boot code from the start address. MPC5566 Microcontroller Reference Manual, Rev. 2 16-14 Freescale Semiconductor...
Page 674 When a valid message is received, the BAM transmits a FlexCAN message with an ID = 0x003 that contains the data received. The host computer must not send another FlexCAN message until MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 675 (specified in step 2). None None The BAM program returns I/O pins and the FlexCAN module to their reset state, then branches to the start address of the stored data (specified in step 2). MPC5566 Microcontroller Reference Manual, Rev. 2 16-16 Freescale Semiconductor...
Page 676: Esci Serial Boot Mode Download Process
Each byte of data received is stored in the MCU’s memory, starting at the address specified in the previous step and incrementing through memory until the number of data bytes received and stored MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 677 The BAM returns I/O pins and the eSCI module to their reset state, except it asserts ESCI_A_CR2[MDIS] instead of negates. Then the BAM branches to the starting address of the stored data specified in step 2. MPC5566 Microcontroller Reference Manual, Rev. 2 16-18 Freescale Semiconductor...
Page 678: Interrupts
Boot Assist Module (BAM) 16.3.3 Interrupts No interrupts are generated or enabled by the BAM. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 16-19...
Page 679 Boot Assist Module (BAM) MPC5566 Microcontroller Reference Manual, Rev. 2 16-20 Freescale Semiconductor...
Page 680: Introduction
Chapter 17 Enhanced Modular Input/Output Subsystem (eMIOS) 17.1 Introduction This chapter describes the enhanced modular input/output subsystem (eMIOS) which can generate or measure timed events. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-1...
Page 681 Note 1: Connection between UC[n-1] and UCn necessary to implement QDEC mode. Note 2: On channels 12–15, there is no input from EMIOS[12:15], only from the DSPI module. Figure 17-1. eMIOS Block Diagram MPC5566 Microcontroller Reference Manual, Rev. 2 17-2 Freescale Semiconductor...
Page 682: Overview
Synchronization among internal and external time bases • Shadow FLAG register • State of module can be frozen for debug purposes • DMA request capability for some channels • Motor control capability MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-3...
Page 683: Emios Operating Modes
• Center-aligned output pulse-width modulation with dead time insertion, buffered • Output pulse-width modulation, normal • Output pulse-width modulation, buffered These modes are described in Section 17.4.4.4, “Unified Channel Operating Modes.” MPC5566 Microcontroller Reference Manual, Rev. 2 17-4 Freescale Semiconductor...
Page 684: External Signal Description
A value of 0 refers to the reset value of the signal. Hi-Z refers to the state of the external pin if a tri-state output buffer is controlled by the corresponding eMIOS signal. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 685: Output Disable Input—Emios Output Disable Input Signals
Output update disable register Base + 0x000C–0x001F — Reserved — Base + 0x0020 Unified channel 0 registers Base + 0x0040 Unified channel 1 registers Base + 0x0060 Unified channel 2 registers MPC5566 Microcontroller Reference Manual, Rev. 2 17-6 Freescale Semiconductor...
Page 686 UCn Base + 0x000C EMIOS_CCRn Channel control register UCn Base + 0x0010 EMIOS_CSRn Channel status register UCn Base + 0x0014 EMIOS_ALTAn Channel alternate address register UCn Base + (0x0018–0x001F) — Reserved — MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-7...
Page 687: Register Description
1 Global time base enable out signal asserted Note: The global time base enable input signal controls the internal counters. When asserted, internal counters are enabled. When negated, internal counters disabled. MPC5566 Microcontroller Reference Manual, Rev. 2 17-8 Freescale Semiconductor...
Page 688: Emios Global Flag Register (Emios_Gfr)
These bits are mirrors of the FLAG bits of each channel register (EMIOS_CSR) and flag bits in those channel registers cannot be cleared by accessing this ‘mirror’ register. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-9...
Page 689: Emios Output Update Disable Register (Emios_Oudr)
B2. OUn bits are used to disable transfers from registers A2 to A1 and B2 to B1. Each bit controls one channel. 0 Transfer enabled. Depending on the operating mode, transfer occurs immediately or in the next period. Unless stated otherwise, transfer occurs immediately. 1 Transfers disabled MPC5566 Microcontroller Reference Manual, Rev. 2 17-10 Freescale Semiconductor...
Page 690: Emios Channel A Data Register (Emios_Cadrn)
The EMIOS_CBDRn must not be read speculatively. For future compatibility, the TLB entry covering the EMIOS_CBDRn must be configured to be guarded. Address: UCn Base + 0x0004 Access: R/W Reset Reset Figure 17-6. eMIOS Channel B Data Register (EMIOS_CBDRn) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-11...
Page 691 — OPWMC – normal — OPWMC – buffered — OPWM – normal — OPWM – buffered — In these modes, the register EMIOS_CBDRn is not used, but B2 can be accessed. MPC5566 Microcontroller Reference Manual, Rev. 2 17-12 Freescale Semiconductor...
Page 692: Emios Channel Counter Register (Emios_Ccntrn)
DMA request enabling, and output mode control. Address: UCn Base + 0x000C Access: R/W FREN ODIS ODISSL UCPRE Reset EDSEL EDPOL MODE FORCMA FORCMB Reset Figure 17-8. eMIOS Channel Control Register (EMIOS_CCRn) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-13...
Page 693 Prescaler. Selects the clock divider value for the unified channel internal prescaler, as shown in the following UCPRE[0:1] table: UCPRE[0:1] Divide Ratio Prescaler enable. Enables the prescaler counter. UCPREN 0 Prescaler disabled (no clock) and prescaler counter is loaded with UCPRE value 1 Prescaler enabled MPC5566 Microcontroller Reference Manual, Rev. 2 17-14 Freescale Semiconductor...
Page 694 DMA request Interrupt Reserved Interrupt Reserved Interrupt Reserved Interrupt Reserved Interrupt DMA request Interrupt DMA request Interrupt DMA request Interrupt DMA request Interrupt Reserved Interrupt Reserved Interrupt Reserved Interrupt Reserved Reserved. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-15...
Page 695 B, otherwise it has no effect. 0 Has no effect 1 Force a match at comparator B For input modes, the FORCMB bit is not used and writing to it has no effect. Reserved. MPC5566 Microcontroller Reference Manual, Rev. 2 17-16 Freescale Semiconductor...
Page 696 For SAOC mode, the EDSEL bit selects the behavior of the output flip-flop at each match. 0 The EDPOL value is transferred to the output flip-flop 1 The output flip-flop is toggled MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-17...
Page 697 0000101 Input period measurement 0000110 Double-action output compare (with FLAG set on the second match) 0000111 Double-action output compare (with FLAG set on both match) 0001000 Pulse and edge accumulation (continuous) MPC5566 Microcontroller Reference Manual, Rev. 2 17-18 Freescale Semiconductor...
Page 698 Output pulse-width modulation. FLAG set at match of internal counter and comparator B, next period update. 0100010 Output pulse-width modulation. FLAG set at match of internal counter and comparator A or comparator B, immediate update. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-19...
Page 699 Center-aligned output pulse-width modulation, buffered. FLAG set on both edges, leading edge dead-time. 1100000 Output pulse-width modulation, buffered. FLAG set on second match. 1100001 Reserved 1100010 Output pulse-width modulation, buffered. FLAG set on both matches. MPC5566 Microcontroller Reference Manual, Rev. 2 17-20 Freescale Semiconductor...
Page 700: Emios Channel Status Register (Emios_Csrn)
FLAG. Set when an input capture or a match event in the comparators occurs. Write a 1 to clear this bit to 0. FLAG 0 FLAG cleared 1 FLAG set event has occurred Note: When EMIOS_CCR[DMA] bit is set, the FLAG bit is cleared by the eDMA controller. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-21...
Page 701: Emios Alternate Address Register (Emios_Altan)
0 to 7 can share counter bus A and B, UCs 8 to 15 can share counter bus A and C, and UCs 16 to 23 can share counter buses A and D. MPC5566 Microcontroller Reference Manual, Rev. 2 17-22...
Page 702: Bus Interface Unit (Biu)
The time slot sequence is 0-1-2-3, such that they alternate between engines one and two. Table 17-13. STAC Client Submodule Server Slot Assignment Engine Time Base Server ID TCR1 TCR2 TCR1 TCR2 MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-23...
Page 703: Effect Of Freeze On The Stac Client Submodule
Counting is enabled by setting EMIOS_MCR[GPREN]. The counter can be stopped at any time by clearing this bit, thereby stopping the internal counter in all the unified channels. MPC5566 Microcontroller Reference Manual, Rev. 2 17-24 Freescale Semiconductor...
Page 704: Unified Channel (Uc)
• Control state machine (FSM) The major components and functions of the unified channels are discussed in Section 17.4.4.1, “Programmable Input Filter (PIF)” through Section 17.4.4.4, “Unified Channel Operating Modes.” MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-25...
Page 705 D for channels 16-23. Refer to Figure 1-1 and EMIOS_CCRn[BS]. 2. Goes to the finite state machine of the UC[n-1]. These signals are used for QDEC mode. Figure 17-13. Unified Channel Block Diagram MPC5566 Microcontroller Reference Manual, Rev. 2 17-26 Freescale Semiconductor...
Page 706: Programmable Input Filter (Pif)
A timing diagram of the input filter is shown in Figure 17-15. Selected clock EMIOSn 5-bit counter IF = 0b0011 Time Filter out Figure 17-15. Programmable Input Filter Example MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-27...
Page 707: Clock Prescaler (Cp)
Section 17.4.4.4.1, “General Purpose Input/Output Mode (GPIO)” through Section 17.4.4.4.14, “Output Pulse-Width Modulation Mode (OPWM) Section 17.4.4.4.18, “Output Pulse-Width Modulation, Buffered Mode (OPWMB)” explain in detail the unified channels’ modes of operation. MPC5566 Microcontroller Reference Manual, Rev. 2 17-28 Freescale Semiconductor...
Page 708: General Purpose Input/Output Mode (Gpio)
Register EMIOS_CADRn returns the value of register A2. The input capture is triggered by a rising, falling or either edges in the input pin, as configured by EDPOL and EDSEL bits in EMIOS_CCR MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-29...
Page 709: Single-Action Output Compare Mode (Saoc)
EMIOS_CADRn returns the value of register A1. An output compare match can be simulated in software by setting the FORCMA bit in EMIOS_CCRn. In this case, the FLAG bit is not set. MPC5566 Microcontroller Reference Manual, Rev. 2 17-30 Freescale Semiconductor...
Page 710: Input Pulse-Width Measurement Mode (Ipwm)
B1 and the trailing edge on register A2. Successive captures are done on consecutive edges of opposite polarity. The leading edge sensitivity (pulse polarity) is selected by EDPOL bit in the MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 711 After input filter. Reading EMIOS_CADRn returns the value of A2, writing EMIOS_CADRn writes to A2. Reading EMIOS_CBDRn returns the value of B1, writing EMIOS_CBDRn writes to B1. Figure 17-19. Input pulse-width Measurement Example MPC5566 Microcontroller Reference Manual, Rev. 2 17-32 Freescale Semiconductor...
Page 712: Input Period Measurement Mode (Ipm)
The IPM mode allows the measurement of the period of an input signal by capturing two consecutive rising edges or two consecutive falling edges. Successive input captures are done on consecutive edges of the same polarity. The edge polarity is defined by the EDPOL bit in the EMIOS_CCRn. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-33...
Page 713 A1 value 0xxxxxxx 0xxxxxxx 0x001000 0x001250 Notes: After input filter. Reading EMIOS_CADRn returns the value of A2. Reading EMIOS_CBDRn returns the value of B1. Figure 17-21. Input Period Measurement Example MPC5566 Microcontroller Reference Manual, Rev. 2 17-34 Freescale Semiconductor...
Page 714: Double-Action Output Compare Mode (Daoc)
B2 must occur and the EMIOS_CCRn[ODIS] bit must be cleared. The output flip-flop is set to the value of EMIOS_CCRn[EDPOL] when a match occurs on comparator A and to the complement of EDPOL when a match occurs on comparator B. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-35...
Page 715 A2 value transferred to A1 according to OUn bit. B2 value transferred to B1 according to OUn bit. Figure 17-23. Double Action Output Compare with FLAG Set on the Second Match MPC5566 Microcontroller Reference Manual, Rev. 2 17-36 Freescale Semiconductor...
Page 716: Pulse/Edge Accumulation Mode (Pea)
EMIOS_CADRn and EMIOS_CBDRn reads do not return coherent data until a new bus capture is triggered to registers A2 and B2. The capture event is indicated when the channel FLAG asserts. If enabled, the FLAG also generates an inter- rupt. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-37...
Page 717 Cleared on the first input event after writing to register A1. After input filter. Writing EMIOS_CADRn writes to A1. Reading EMIOS_CADRn returns the value of A2. Reading EMIOS_CBDRn returns the value of B1. Figure 17-25. Pulse/Edge Accumulation Continuous Mode Example MPC5566 Microcontroller Reference Manual, Rev. 2 17-38 Freescale Semiconductor...
Page 718: Pulse And Edge Counting Mode (Pec)
A1, when a match occur between comparator A and the selected timebase, the internal counter is cleared and it is ready to start counting input events. When the time base matches comparator B1, the MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 719 0x000303 0x000303 EMIOS_CCNTRn EMIOS_CCNTRn A2 value Notes: Writing EMIOS_CADRn writes to A1. Writing EMIOS_CBDRn writes to B1. Reading EMIOS_ALTAn returns the value of A2. Figure 17-27. Pulse/Edge Counting Continuous Mode Example MPC5566 Microcontroller Reference Manual, Rev. 2 17-40 Freescale Semiconductor...
Page 720: Quadrature Decode Mode (Qdec)
UCn EDPOL bit selects count direction according to direction signal and UC[n-1] EDPOL bit selects if the internal counter is clocked by the rising or falling edge of the count signal. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 721 A1 match A1 match EMIOS_CCNTRn Value 2 Value 1 0x000000 Time FLAG set event Note: Writing EMIOS_CADRn writes to A1. Figure 17-30. Quadrature Decode Mode Example with Phase_A and Phase_B Encoder MPC5566 Microcontroller Reference Manual, Rev. 2 17-42 Freescale Semiconductor...
Page 722: Windowed Programmable Time Accumulation Mode (Wpta)
In WPTA mode this register is accessible through the alternate register address EMIOS_ALTAn. NOTE The FORCMA and FORCMB bits have no effect when the unified channel is configured for WPTA mode. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-43...
Page 723: Modulus Counter Mode (Mc)
B1, internal clock source. 0b0010101 Modulus counter. Up/down counter, no change in counter direction upon match of input counter and register B1, external clock source. MPC5566 Microcontroller Reference Manual, Rev. 2 17-44 Freescale Semiconductor...
Page 724 MC mode. NOTE Any update to the A register takes place immediately, regardless of the current state of the counter and whether the counter is in up mode, or up/down mode. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-45...
Page 725 A1 value 0xxxxxxx 0x000303 0x000303 0x000200 0x000200 0x000200 Notes: Writing EMIOS_An writes to A2. A2 value transferred to A1 according to OUn bit. Figure 17-33. Modulus Counter Up/Down Mode Example MPC5566 Microcontroller Reference Manual, Rev. 2 17-46 Freescale Semiconductor...
Page 726 1. If not currently stored, store value of register A. 2. Set A=B. 3. If immediate 0% duty cycle is desired, set FORCA=1. 4. To return to the previous duty cycle, restore register A with its former value. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-47...
Page 727 Writing EMIOS_An writes to A2. Writing EMIOS_Bn writes to B2. A2 value transferred to A1 according to OUn bit. B2 value transferred to B1 according to OUn bit. Figure 17-34. OPWFM with Immediate Update MPC5566 Microcontroller Reference Manual, Rev. 2 17-48 Freescale Semiconductor...
Page 728 Writing EMIOS_An writes to A2. Writing EMIOS_Bn writes to B2. A2 value transferred to A1 according to OUn bit. B2 value transferred to B1 according to OUn bit. Figure 17-35. OPWFM with Next Period Update MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-49...
Page 729 Table 17-25. Examples of Output Waveforms EDPOL Duty Cycle Waveform (decimal) (decimal) 1000 1000 1000 1000 Active high output 1000 100% 1000 1000 1000 1000 1000 Active low output 1000 100% 1000 MPC5566 Microcontroller Reference Manual, Rev. 2 17-50 Freescale Semiconductor...
Page 730 EDPOL bit and the time base is switched to the selected counter bus. This sequence repeats continuously. FLAG can be generated in the trailing edge of the output PWM signal when MODE[5] is cleared, or in both edges, when MODE[5] is set. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-51...
Page 731 MODE[5] bit. NOTE If A1 and B1 are set to the 0x000000, a 0% duty cycle waveform is produced. NOTE Any updates to the A or B register takes place immediately. MPC5566 Microcontroller Reference Manual, Rev. 2 17-52 Freescale Semiconductor...
Page 732 Writing EMIOS_Bn writes to B1. A2 value transferred to A1 according to OUn bit. B2 value transferred to B1 according to OUn bit. Figure 17-36. Output PWMC with Leading Dead-time Insertion MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-53...
Page 733: Output Pulse-Width Modulation Mode (Opwm)
Output pulse-width modulation. FLAG set at match of internal counter and comparator A or comparator B, immediate update. 0b0100011 Output pulse-width modulation. FLAG set at match of internal counter and comparator A or comparator B, next period update. MPC5566 Microcontroller Reference Manual, Rev. 2 17-54 Freescale Semiconductor...
Page 734 NOTE Updates to the A register always occur immediately. If next period update is selected via the mode[6] bit, only the B register update is delayed until the next period. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-55...
Page 735 Writing EMIOS_Bn writes to B2. A2 value transferred to A1 according to OUn bit. B2 value transferred to B1 according to OUn bit. Figure 17-39. Output PWM with Next Period Update MPC5566 Microcontroller Reference Manual, Rev. 2 17-56 Freescale Semiconductor...
Page 736: Modulus Counter Buffered Mode (Mcb)
The MCB mode counts between one and the A1 register value. The counter cycle period in up count mode is equal to the A1 value. In up/down counter mode the period is defined by the formula: (2 × A1) – 2. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 737 FLAG set event 0x000005 0x000007 A2 value A1 value 0x000006 0x000005 0x000007 Note: A2 value transferred to A1 according to OUn bit. Figure 17-41. eMIOS MCB Mode Example — Up/Down Operation MPC5566 Microcontroller Reference Manual, Rev. 2 17-58 Freescale Semiconductor...
Page 738 Note: A2 value transferred to A1 according to OUn bit (the transfer is triggered by the A1 load signal). Figure 17-43. eMIOS MCB Mode Example — Up/Down Operation A1 Register Update MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-59...
Page 739 For example, if register A1 is set to 0x000004, the output flip-flop transitions 4 counter periods after the cycle starts, plus one system clock cycle. In the example shown in Figure 17-44 the prescaler ratio is set to two (refer to Section 17.5.3, “Time Base Generation). MPC5566 Microcontroller Reference Manual, Rev. 2 17-60 Freescale Semiconductor...
Page 740 Edge detection B1 match B1 match negative edge detect B1 match negative Edge detection Output flip-flop EDPOL = 0 Figure 17-44. eMIOS OPWFMB Mode Example — A1/B1 Match to Output Register Delay MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-61...
Page 741 B1 match negative B1 Match negative edge detect edge Detection Output flip-flop No transition at this point EDPOL = 0 Figure 17-45. eMIOS OPWFMB Mode Example — A1 = 0 (0% Duty Cycle) MPC5566 Microcontroller Reference Manual, Rev. 2 17-62 Freescale Semiconductor...
Page 742 A1/B1 load signal 0x000004 0x000006 A1 value 0x000002 0x000002 0x000004 0x000006 A2 value B1 value 0x000008 0x000006 B2 value 0x000008 0x000006 Figure 17-46. eMIOS OPWFMB Mode Example — A1/B1 Updates and Flags MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-63...
Page 743 A or B respectively. Similar to a B1 match, FORCMB clears the internal counter. The FLAG bit is not set when the FORCMA or FORCMB bits are set. MPC5566 Microcontroller Reference Manual, Rev. 2 17-64...
Page 744 Register A1 contains the ideal duty cycle for the PWM signal and is compared with the selected time base. Register B1 contains the dead time value and is compared against the internal counter. For a leading edge MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 745 B1 and the internal time base, the output flip-flop is set to the value of the EDPOL bit. In the following match between A1 and the selected time base, the output flip-flop is set to the complement of the EDPOL bit. This sequence repeats continuously. MPC5566 Microcontroller Reference Manual, Rev. 2 17-66 Freescale Semiconductor...
Page 746 Internal counter is set to 1 on A1 match 0x000004 0x000002 0x000001 Time Dead-time Dead-time Output flip-flop FLAG set event Figure 17-50. eMIOS PWMCB Mode Example — Lead Dead Time Insertion MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-67...
Page 747 FORCMA sets the output flip-flop to the compliment of EDPOL. In trailing dead time insertion mode, the output flip-flop is forced to the value of EDPOL. MPC5566 Microcontroller Reference Manual, Rev. 2 17-68 Freescale Semiconductor...
Page 748 (n+1). In this case the B1 match is masked out and does not cause the output flip-flop to transition. Therefore matches in cycle (n+1) are not affected by the late B1 matches from cycle (n). MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 749 A1 or B1. Refer to Figure 17-44, which illustrates the delay from matches to output flip-flop transition in OPWFMB mode. MPC5566 Microcontroller Reference Manual, Rev. 2 17-70 Freescale Semiconductor...
Page 750: Output Pulse-Width Modulation, Buffered Mode (Opwmb)
Values written to A2 or B2 on cycle (n) are loaded to A1 or B1 at the following cycle boundary (assuming EMIOS_OUDR[n] is not asserted). Thus the new values are used for A1 and B1 matches in cycle (n+1). MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-71...
Page 751 A1 being set to zero in cycle (n+1). In this case the match positive edge is used instead of the negative edge to transition the output flip-flop. MPC5566 Microcontroller Reference Manual, Rev. 2 17-72 Freescale Semiconductor...
Page 752 B1 match B1 match negative B1 match negative edge detect edge detection Output flip-flop EDPOL = 0 FLAG bit set Figure 17-54. eMIOS OPWMB Mode Example — 0% Duty Cycle MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-73...
Page 753 EDPOL at B1 matches. In this example, if B1 = 0x000009, a B1 match does not occur, and thus a 0% duty cycle signal is generated. MPC5566 Microcontroller Reference Manual, Rev. 2 17-74 Freescale Semiconductor...
Page 754: Initialization/Application Information
Figure 17-58, Figure 17-59, and Figure 17-57 illustrate the time base generation mechanism. Figure 17-60 shows the time base generation when using the internal clock set and clear on match start. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-75...
Page 755 Initial time base period The next clock cycle clears includes the match value. Match occurs the internal counter, starting another period. Figure 17-58. eMIOS Time Base Example — Fastest Prescaler Ratio = 1 MPC5566 Microcontroller Reference Manual, Rev. 2 17-76 Freescale Semiconductor...
Page 756 Note 1: When a match occurs, the first clock cycle is used to clear the internal counter. The internal counter starts counting after the second edge of the prescaled clock. Figure 17-60. Time Base Generation Using the Internal Clock with Clear on Match Start MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 17-77...
Page 757 Enhanced Modular Input/Output Subsystem (eMIOS) MPC5566 Microcontroller Reference Manual, Rev. 2 17-78 Freescale Semiconductor...
Page 758: Introduction
Chapter 18 Enhanced Time Processing Unit (eTPU) 18.1 Introduction The enhanced time processing unit (eTPU) operates in parallel with the MPC5566 core (CPU) to: • Execute programs independently from the host core • Detect and precisely record the timing of input events •...
Page 759: Block Diagram
Enhanced Time Processing Unit (eTPU) Because of the differences between the MPC5566 implementation of the eTPU and the full eTPU, full register bit descriptions are included within this chapter as well as in the Enhanced Time Processing (eTPU) Reference Manual.
Page 760: Etpu Operation Overview
Function routines, which reside in the SCM, are also used to configure the channel. A function can be assigned to several channels, but a channel can only process MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 761: Etpu Engine
TCRCLK pin. In addition, the TCR2 time base can be derived from special angle-clock hardware that enables implementing angle-based functions. This feature is added to support advanced angle-based engine control applications. MPC5566 Microcontroller Reference Manual, Rev. 2 18-4 Freescale Semiconductor...
Page 762: Etpu Timer Channels
NOTE The host transfers the code image for the eTPU microcode to the SCM, then the host enables eTPU access to the SCM (which also disables host access). MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 18-5...
Page 763: Shared Data Memory (Sdm)
Reads return the lower 3-bytes of a word sign-extended to 32 bits; the most significant bit of the word’s second most significant byte (byte addresses) is copied in all 8 bits of the most significant read byte. MPC5566 Microcontroller Reference Manual, Rev. 2 18-6...
Page 764: Task Scheduler
The scheduler determines the order in which channels are serviced based on channel number and assigned priority. The priority mechanism, implemented in hardware, ensures that all requesting channels are serviced. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 18-7...
Page 765: Microengine
18.1.4.7 Dual eTPU Engine System The MPC5566 eTPU implementation includes two eTPU engines sharing SDM and the same code in the SCM. The two eTPU engines share the bus interface unit (BIU) and the shared data memory (SDM). This allows the MPC5566 core to communicate with the eTPU and also provides a means of communication between the eTPU engines.
Page 766 — Two-system-clock microcycle fixed-length instruction execution for the ALU. — 20 KB of shared code memory (SCM). — Interleaved SCM access in dual-engine eTPU (MPC5566) avoids contention in time for instruction memory. — 4 KB of shared data memory (SDM) —...
Page 767: Modes Of Operation
— SCM (code memory) continuous signature-check built-in code integrity test multiple input signature calculator (MISC): runs concurrently with eTPU normal operation 18.2 Modes of Operation The eTPU is capable of working in the following modes. MPC5566 Microcontroller Reference Manual, Rev. 2 18-10 Freescale Semiconductor...
Page 768: User Configuration Mode
(there is one ETPU_ECR for each engine). 18.3 External Signal Description 18.3.1 Overview There are a total 65 external signals in each eTPU engine: • 32 channel input signals • 32 channel output signals MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 18-11...
Page 769: Output And Input Channel Signals
The channel numbers for some of the DSPI channels connections are reversed, for example if eTPU_B[0:7] is mapped to DSPI_A[15:8], then eTPU_B[0] is connected to DSPI_A[15], eTPU_B[1] is connected to DSPI_A[14],..., eTPU_B[7] is connected to DSPI_A[8]. MPC5566 Microcontroller Reference Manual, Rev. 2 18-12 Freescale Semiconductor...
Page 770: Time Base Clock Signal (Tcrclka And Tcrclkb)
Refer to Section 17.2.1.1, “Output Disable Input—eMIOS Output Disable Input Signals,” for more information on the output disable signals. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 18-13...
Page 771: Memory Map And Register Definition
B channel registers Base + (0x0000_0C00–0x0000_7FFF) Reserved Base + (0x0000_8000–0x0000_8FFF) Shared data memory (4 KB) Base + (0x0000_9000–0x0000_BFFF) Reserved Base + (0x0000_C000–0x0000_CFFF) Shared data memory PSE mirror (4 KB) Base + (0x0000_CD00–0x0000_FFFF) Reserved MPC5566 Microcontroller Reference Manual, Rev. 2 18-14 Freescale Semiconductor...
Page 772: Etpu Register Addresses
Base + (0x0000_0050–0x0000_01FF) — Reserved — Base + 0x0000_0200 ETPU_CISR_A eTPU A channel interrupt status register Base + 0x0000_0204 ETPU_CISR_B eTPU B channel interrupt status register Base + 0x0000_0208 — Reserved — MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 18-15...
Page 773 Base + 0x0000_028C — Reserved — Base + 0x0000_0290 ETPU_CSSR_A eTPU A channel service status register Base + 0x0000_0294 ETPU_CSSR_B eTPU B channel service status register Base + (0x0000_0298–0x0000_03FF) — Reserved — MPC5566 Microcontroller Reference Manual, Rev. 2 18-16 Freescale Semiconductor...
Page 774 Base + (0x0000_8000–0x0000_8BFF) Shared Data Memory (parameter RAM) 4 KB Base + (0x0000_8C00–0x0000_BFFF) — Reserved — Base + (0x0000_C000–0x0000_CBFF) — SDM PSE mirror 4 KB Base + (0x0000_CC00–0x0000_FFFF) — Reserved — MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 18-17...
Page 775: System Configuration Registers
Reserved — The register at this address is available only on the MPC5554 and the MPC5566. Parameter sign extension access area. Refer to the eTPU Reference Manual. SCM access is only available under certain conditions when ETPU_MCR[VIS] = 1. The SCM can only be written in 32-bit accesses.
Page 776 1 MISC operation enabled. (Toggling to 1 clears the SCMMISF bit) SCMMISEN is cleared automatically when MISC logic detects an error; that is, when SCMMISF transitions from 0 to 1, disabling the MISC operation. 23–24 Reserved MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 18-19...
Page 777: Etpu Coherent Dual-Parameter Controller Register (Etpu_Cdcr)
ETPU_CDCR configures and controls dual-parameter coherent transfers. For more information, refer to the eTPU Reference Manual. Address: Base + 0x0000_0004 Access: R/W CTBASE PBBASE Reset R PWID PARM0 PARM1 Reset Figure 18-6. eTPU Coherent Dual-Parameter Controller Register (ETPU_CDCR) MPC5566 Microcontroller Reference Manual, Rev. 2 18-20 Freescale Semiconductor...
Page 778 SDM base) of the parameter which is the destination or source (defined by WR) of the coherent transfer. The SDM PARM1 address offset of the parameter is {CTBASE, PARM1}*4. PARM1 allows non-contiguous parameters to be [0:6] transferred coherently The parameter pointed by {CTBASE, PARM0} is the first transferred. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 18-21...
Page 779: Etpu Misc Compare Register (Etpu_Misccmpr)
The ETPU_SCMOFFDATAR reset value is the opcode of an instruction that disables matches, clears the TDLs and the MRLs; the opcode also issues an illegal instruction Global Exception, and ends the thread. MPC5566 Microcontroller Reference Manual, Rev. 2 18-22 Freescale Semiconductor...
Page 780: Etpu Engine Configuration Register (Etpu_Ecr)
Address: Base + 0x0000_0014 (eTPU A) Access: R/W Address: Base + 0x0000_0018 (eTPU B) HLTF FEND MDIS FPSCK Reset CDFC Reset Figure 18-9. eTPU Engine Configuration Register (ETPU_ECR) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 18-23...
Page 781 Refer to the eTPU Reference Manual for further details about entering halt mode. HLTF 0 eTPU engine is not halted. 1 eTPU engine is halted 9–12 Reserved MPC5566 Microcontroller Reference Manual, Rev. 2 18-24 Freescale Semiconductor...
Page 782 For more information on filtering, refer to the eTPU Reference Manual. Changing CDFC during eTPU normal input channel operation is not recommended since it changes the behavior of the transition detection logic while executing its operation. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 18-25...
Page 783: Time Base Registers
TCR2. There is one of each of these registers for each eTPU engine. NOTE Writes to this register generate a bus error and are ineffective when MDIS = 1. Reads are always permitted. MPC5566 Microcontroller Reference Manual, Rev. 2 18-26 Freescale Semiconductor...
Page 784: Etpu Time Base Configuration Register (Etpu_Tbcr)
TCR2CTL TCRCF TCR2P Reset TCR1CTL TCR1P Reset Figure 18-10. eTPU Time Base Configuration Register (ETPU_TBCR) NOTE The MPC5566 has two eTPU engines, each with a dedicated TCRCLK signal: TCRCLKA and TCRCLKB. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 18-27...
Page 785 Two sample TCRCF Filter clock of the channels Two sample System clock divided by 2 Integration Filter clock of the channels Integration For more information, refer to the eTPU Reference Manual. Reserved MPC5566 Microcontroller Reference Manual, Rev. 2 18-28 Freescale Semiconductor...
Page 786 2 or the output of TCRCLK filter, or Peripheral Timebase input. TCR1P The prescaler divides this input by (TCR1P+1) allowing frequency divisions from 1 up to 256. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 18-29...
Page 787: Etpu Time Base 1 (Tcr1) Visibility Register (Etpu_Tb1R)
Figure 18-11. eTPU Time Base 1 (TCR1) Visibility Register (ETPU_TB1R) Table 18-12. ETPU_TB1R Field Descriptions Field Description 0–7 Reserved 8–31 TCR1 value. Used on matches and captures. For more information, refer to the eTPU Reference Manual. TCR1 [0:23] MPC5566 Microcontroller Reference Manual, Rev. 2 18-30 Freescale Semiconductor...
Page 788: Etpu Time Base 2 (Tcr2) Visibility Register (Etpu_Tb2R)
Figure 18-12. eTPU Time Base 2 (TCR2) Visibility Register (ETPU_TB2R) Table 18-13. ETPU_TB2R Bit Field Descriptions Field Description 0–7 Reserved 8–31 TCR2 value. Used on matches and captures. For information on TCR2, refer to the eTPU Reference Manual. TCR2 [0:23] MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 18-31...
Page 789: Stac Bus Configuration Register (Etpu_Redcr)
Enables or disables client/server operation for eTPU slave resources. REN2 enables TCR2 slave bus operations. REN2 1 Server/client operation for resource 2 is enabled. 0 Server/client operation for resource 2 is disabled. MPC5566 Microcontroller Reference Manual, Rev. 2 18-32 Freescale Semiconductor...
Page 790: Global Channel Registers
For more information, refer to Section 18.4.6.3, “eTPU Channel n Status Control Register (ETPU_CnSCR),” and the eTPU Reference Manual. NOTE The host core must write 1 to clear (w1c) an interrupt status bit. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 18-33...
Page 791: Etpu Channel Data Transfer Request Status Register (Etpu_Cdtrsr)
For more information on data transfers and channel control registers, refer to the eTPU Reference Manual. In the MPC5566, eTPU A channels [0:2,12:15,28:29] and eTPU B channels [0:3,12:15,28:31] are connected to the DMA. The data transfer request lines...
Page 792: Etpu Channel Interrupt Overflow Status Register (Etpu_Ciosr)
Section 18.4.6.3, “eTPU Channel n Status Control Register (ETPU_CnSCR),” and the eTPU Reference Manual. NOTE The host must write 1 to clear an interrupt overflow status bit. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 18-35...
Page 793 Section 18.4.6.3, “eTPU Channel n Status Control Register (ETPU_CnSCR),” and the eTPU Reference Manual. NOTE The host must write 1 to clear a data transfer request overflow status bit. MPC5566 Microcontroller Reference Manual, Rev. 2 18-36 Freescale Semiconductor...
Page 794: Etpu Channel Interrupt Enable Register (Etpu_Cier)
The host interrupt enable bits for all 32 channels are grouped in ETPU_CIER. The bits are mirrored by the channel configuration registers. For more information on channel configuration registers and interrupt enable, refer to Section 18.4.6.2, “eTPU Channel n Configuration Register (ETPU_CnCR),” and the eTPU Reference Manual. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 18-37...
Page 795: Etpu Channel Data Transfer Request Enable Register (Etpu_Cdtrer)
Figure 18-18. eTPU Channel Interrupt Enable Register (ETPU_CIER) Table 18-19. ETPU_CIER Field Descriptions Field Description Channel n interrupt enable. Enable the eTPU channels to interrupt the MPC5566 core. 0–31 0 Interrupt disabled for channel n. CIEn 1 Interrupt enabled for channel n For details about interrupts refer to the eTPU Reference Manual.
Page 796: Etpu Channel Pending Service Status Register (Etpu_Cpssr)
1 pending service request for channel n NOTE The pending service status bit for a channel is set when a service request is pending, even if the Channel is disabled (CPRn = 0). MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 18-39...
Page 797: Etpu Channel Service Status Register (Etpu_Cssr)
Channel Configuration and Control Registers Each channel, for both eTPU engines, has a group of three registers used to control, configure and check status of that channel as shown in Table 18-23. MPC5566 Microcontroller Reference Manual, Rev. 2 18-40 Freescale Semiconductor...
Page 798: Channel Registers Layout
(ETPU_CnHSRR) 0x000C Reserved In the MPC5566, eTPU A channels [0:2,12:15,28:29] and eTPU B channels [0:3,12:15,28:31] are connected to the DMA. The data transfer request lines that are not connected to the DMA controller are left disconnected and do not generate interrupt requests, even if their request status bits assert in registers ETPU_CDTRSR and ETPU_CnSCR.
Page 799: Etpu Channel N Configuration Register (Etpu_Cncr)
ETPD ETCS Reset ODIS OPOL CPBA Reset ETPD is not available on the MPC5566. Figure 18-22. ETPU Channel n Configuration Register (ETPU_CnCR Table 18-25. ETPU_CnCR Field Descriptions Field Description Channel interrupt enable. This bit is mirrored from the ETPU_CIER 0 Disable interrupt for this channel.For more information, refer to the eTPU Reference Manual.
Page 800: Etpu Channel N Status Control Register (Etpu_Cnscr)
(read-write). Bits CIS, CIOS, DTRS, and DTROS for each channel can also be accessed from ETPU_CISR, ETPU_CIOSR, ETPU_CDTRSR, and ETPU_CDTROSR respectively. For more information on the three previously mentioned registers, refer to the eTPU Reference Manual. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 18-43...
Page 801 DTRS is mirrored in the ETPU_CDTRSR. For more information on the ETPU_CDTRSR and data transfer, refer to DTRS Section 18.4.5.2, “eTPU Channel Data Transfer Request Status Register (ETPU_CDTRSR)” and the eTPU Reference Manual. The core must write 1 to clear DTRS. MPC5566 Microcontroller Reference Manual, Rev. 2 18-44 Freescale Semiconductor...
Page 802: Etpu Channel N Host Service Request Register (Etpu_Cnhsrr)
ETPU_CnHSRR is used by the device core to issue service requests to the channel. Address: Channel_Register_Base + 0x0008 Access: R/W Reset Reset Figure 18-24. eTPU Channel n Host Service Request Register (ETPU_CnHSRR) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 18-45...
Page 803: Functional Description
After initial power-on reset, the eTPU remains in an idle state (except when debug is asserted on power-on reset—in this case, the microengines awaken in the halt state). In addition, initialize the SCM with the eTPU application prior to configuring the eTPU. MPC5566 Microcontroller Reference Manual, Rev. 2 18-46 Freescale Semiconductor...
Page 804: Introduction
The eQADC provides a parallel interface to two on-chip analog-to-digital converters (ADCs), and a single master to single slave serial interface to an off-chip external device. The two on-chip ADCs are architected to allow access to all the analog channels. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-1...
Page 805: Block Diagram
CFIFOs to the on-chip ADCs or to the external device. (Refer to Section 6.4.5.1, “eQADC External Trigger Input Multiplexing.”) It also monitors the amount of memory currently in use by each the CFIFO and RFIFO to detect underflow and overflow conditions. MPC5566 Microcontroller Reference Manual, Rev. 2 19-2 Freescale Semiconductor...
Page 806 RFIFO. When data is stored in an RFIFO, data is moved from the RFIFO by the host CPU or by the eDMA to a data structure in system memory depicted in Figure 19-1 as a user-defined result queue. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-3...
Page 807: Features
— Generates interrupt when command coherency is not achieved. • External hardware triggers — Supports rising edge, falling edge, high level and low level triggers — Supports configurable digital filter • Upgrades the functionality of the QADC 1. V MPC5566 Microcontroller Reference Manual, Rev. 2 19-4 Freescale Semiconductor...
Page 808: Modes Of Operation
• Command transfer is in progress. eQADC completes the transfer and updates CFIFO status before halting future command transfers from any CFIFO. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-5...
Page 809: Stop Mode
If valid data (conversion result or data read from an ADC register) is received at the end of the transmission, it is not sent to an RFIFO until stop mode exits. MPC5566 Microcontroller Reference Manual, Rev. 2 19-6...
Page 810: External Signal Description
Single-ended analog input 4 I / — AN[4] / — Analog DAN2+ Positive terminal differential input AN[5]_ Single-ended analog input 5 I / — AN[5] / — Analog DAN2- Negative terminal differential input MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-7...
Page 811 Single-ended analog input I / — AN[26] / — Analog AN[27:28] / AN[27:28] Single-ended analog input I / — Analog — AN[29] Single-ended analog input I / — AN[29] / — Analog MPC5566 Microcontroller Reference Manual, Rev. 2 19-8 Freescale Semiconductor...
Page 812: Memory Map And Register Definition
This section provides memory maps and detailed descriptions of all registers. Data written to or read from reserved areas of the memory map is undefined. 19.3.1 eQADC Memory Map This section provides memory maps for the eQADC. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-9...
Page 813 Base + 0x0066 EQADC_IDCR3 eQADC interrupt and eDMA control register 3 Base + 0x0068 EQADC_IDCR4 eQADC interrupt and eDMA control register 4 Base + 0x006A EQADC_IDCR5 eQADC interrupt and eDMA control register 5 MPC5566 Microcontroller Reference Manual, Rev. 2 19-10 Freescale Semiconductor...
Page 814 — Reserved — Base + (0x0180–0x018C) EQADC_CF2Rn eQADC CFIFO2 registers 0–3 Base + (0x0190–0x01BC) — Reserved — Base + (0x01C0–0x01CC) EQADC_CF3Rn eQADC CFIFO3 registers 0–3 Base + (0x01D0–0x01FC) — Reserved — MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-11...
Page 815: Eqadc Register Descriptions
Register Descriptions 19.3.2.1 eQADC Module Configuration Register (EQADC_MCR) The EQADC_MCR contains bits used to control how the eQADC responds to a debug mode entry request, and to enable the eQADC SSI interface. MPC5566 Microcontroller Reference Manual, Rev. 2 19-12 Freescale Semiconductor...
Page 816: Eqadc Null Message Send Format Register (Eqadc_Nmsfr)
When disabling the eQADC SSI, the FCK does not stop until it reaches its low phase. 19.3.2.2 eQADC Null Message Send Format Register (EQADC_NMSFR) The EQADC_NMSFR defines the format of the null message sent to the external device. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-13...
Page 817: Eqadc External Trigger Digital Filter Register (Eqadc_Etdfr)
The EQADC_ETDFR is used to set the minimum time a signal must be held in a logic state on the CFIFO triggers inputs to be recognized as an edge or level gated trigger. The digital filter length field specifies the MPC5566 Microcontroller Reference Manual, Rev. 2 19-14...
Page 818 DFL[0:3] Minimum Clock Count (System Clock = 120MHz) 0b0000 16.67 0b0001 25.00 0b0010 41.67 0b0011 75.00 0b0100 141.67 0b0101 275.00 0b0110 541.67 0b0111 1075.00 0b1000 2141.67 0b1001 4275.00 0b1010 1025 8541.67 MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-15...
Page 819: Eqadc Cfifo Push Registers 0–5 (Eqadc_Cfprn)
Note: Write only whole words to the EQADC_CFPRn registers. Writing halfwords or bytes to EQADC_CFPR pushes the entire 32-bit CF_PUSH field into the CFIFO, but undefined data fills the areas of CF_PUSH that were not specifically designated as target locations for the write. MPC5566 Microcontroller Reference Manual, Rev. 2 19-16 Freescale Semiconductor...
Page 820: Eqadc Result Fifo Pop Registers 0–5 (Eqadc_Rfprn)
RFCTRn value. Writing to EQADC_RFPRn has no effect. 19.3.2.6 eQADC CFIFO Control Registers 0–5 (EQADC_CFCRn) The eQADC_CFCRs contain bits that affect CFIFOs. These bits specify the CFIFO operation mode and can invalidate all of the CFIFO contents. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-17...
Page 821 Table 19-10. CFIFO Operation Mode Table MODEn[0:3] CFIFO Operation Mode 0b0000 Disabled 0b0001 Software trigger, single scan 0b0010 Low level gated external trigger, single scan 0b0011 High level gated external trigger, single scan MPC5566 Microcontroller Reference Manual, Rev. 2 19-18 Freescale Semiconductor...
Page 822: Eqadc Interrupt And Edma Control Registers 0–5 (Eqadc_Idcrn)
EQADC_BASE + 0x0064 (EQADC_IDCR2) EQADC_BASE + 0x0066 (EQADC_IDCR3) EQADC_BASE + 0x0068 (EQADC_IDCR4) EQADC_BASE + 0x006A (EQADC_IDCR5) R NCI TORI EOQI CFUI RFOI PIEn Reset Figure 19-8. eQADC Interrupt and eDMA Control Registers 0–5 (EQADC_IDCRn) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-19...
Page 823 0 Generate interrupt request to move data from the system memory to CFIFOn. 1 Generate eDMA request to move data from the system memory to CFIFOn. Note: CFFSn must not be negated while an eDMA transaction is in progress. MPC5566 Microcontroller Reference Manual, Rev. 2 19-20 Freescale Semiconductor...
Page 824 0 Generate interrupt request to move data from RFIFn to the system memory 1 Generate eDMA request to move data from RFIFOn to the system memory Note: RFDSn must not be negated while an eDMA transaction is in progress. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-21...
Page 825: Eqadc Fifo And Interrupt Status Registers 0–5 (Eqadc_Fisrn)
Write 1 to clear the TORFn bit. Writing 0 has no effect. 0 No trigger overrun occurred 1 Trigger overrun occurred Note: The trigger overrun flag is not set for CFIFOs configured for software trigger mode. MPC5566 Microcontroller Reference Manual, Rev. 2 19-22 Freescale Semiconductor...
Page 826 Note: An asserted EOQFn only implies that the eQADC has finished transferring a command with an asserted EOQ bit from CFIFOn. It does not imply that result data for the current command and for all previously transferred commands has been returned to the appropriate RFIFO. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-23...
Page 827 Note: When generation of interrupt requests is selected (CFFSn=0), CFFFn must only be cleared in the ISR after the CFIFOn push register is accessed. Note: CFFFn should not be cleared when CFFSn is asserted (eDMA requests selected). 7–11 Reserved. MPC5566 Microcontroller Reference Manual, Rev. 2 19-24 Freescale Semiconductor...
Page 828 EQADC_RFPRn is read. If the maximum index number (RFIFO depth minus 1) is reached, [0:3] POPNXTPTRn is wrapped to 0, else, it is incremented by 1. For details refer to Section 19.4.4.1, “RFIFO Basic Functionality.” Writing any value to POPNXTPTRn has no effect. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-25...
Page 829: Eqadc Cfifo Transfer Counter Registers 0–5 (Eqadc_Cftcrn)
CFIFO. The EQADC_CFSSRs are read only. Writing to the EQADC_CFSSRs has no effect. MPC5566 Microcontroller Reference Manual, Rev. 2 19-26 Freescale Semiconductor...
Page 830 TC_LCFT0 is a copy of the corresponding TC_CFn in EQADC_CFTCRn (see Section 19.3.2.9) captured at the time a command transfer from CFIFOn to ADCn command buffer is initiated. This field has no meaning when LCFT0 is 0b1111. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-27...
Page 831 “eQADC CFIFO Transfer Counter Registers 0–5 (EQADC_CFTCRn)”) captured at the time a command transfer from CFIFOn to ADCn command buffer is initiated. This field has no meaning when LCFT1 is 0b1111. MPC5566 Microcontroller Reference Manual, Rev. 2 19-28 Freescale Semiconductor...
Page 832 External command buffer number Indicator. Indicates to which external command buffer the last command was transmitted. 0 Last command was transferred to command buffer 2. 1 Last command was transferred to command buffer 3. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-29...
Page 833: Eqadc Cfifo Status Register (Eqadc_Cfsr)
The EQADC_CFSR contains the current CFIFO status. The EQADC_CFSRs are read only. Writing to the EQADC_CFSR has no effect. Address: Base + 0x00AC Access: RO CFS0 CFS1 CFS2 CFS3 CFS4 CFS5 Reset Reset Figure 19-14. eQADC CFIFO Status Register (EQADC_CFSR) MPC5566 Microcontroller Reference Manual, Rev. 2 19-30 Freescale Semiconductor...
Page 834: Eqadc Ssi Control Register (Eqadc_Ssicr)
0b11 CFIFO is triggered 19.3.2.12 eQADC SSI Control Register (EQADC_SSICR) The EQADC_SSICR configures the SSI submodule. Address: Base + 0x00B4 Access: R/W Reset Reset Figure 19-15. eQADC SSI Control Register (EQADC_SSICR) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-31...
Page 835 0b001 0b010 0b011 0b100 0b101 0b110 0b111 Table 19-21. System Clock Divide Factor for Baud Clock BR[0:3] System Clock Divide Factor 0b0000 0b0001 0b0010 0b0011 0b0100 0b0101 0b0110 0b0111 0b1000 0b1001 MPC5566 Microcontroller Reference Manual, Rev. 2 19-32 Freescale Semiconductor...
Page 836: Eqadc Ssi Receive Data Register (Eqadc_Ssirdr)
DATA. Contains the last result message that was shifted in. Writes to the R_DATA have no effect. R_DATA Messages that were not completely received due to a transmission abort is not copied into EQADC_SSIRDR. [0:25] MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-33...
Page 837: Eqadc Cfifo Registers (Eqadc_Cf[0–5]Rn)
CFIFO[0–5]_datan. Returns the value stored within the entry of CFIFO[0–5]. Each CFIFO is composed of four CFIFO[0–5] 32-bit entries, with register 0 being mapped to the entry with the smallest memory mapped address. _DATAn [0:31] MPC5566 Microcontroller Reference Manual, Rev. 2 19-34 Freescale Semiconductor...
Page 838: Eqadc Rfifo Registers (Eqadc_Rf[0–5]Rn)
RFIFO[0–5] data n. Returns the value stored within the entry of RFIFO[0–5]. Each RFIFO is composed of four _DATAn 16-bit entries, with register 0 being mapped to the entry with the smallest memory mapped address. [0:15] MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-35...
Page 839: On-Chip Adc Registers
This register is also accessible by configuration commands sent to the ADC1 command buffer. Table 19-26. ADC1 Registers ADC1 Register Access Address 0x0000 ADC1 Address 0x00 is used for conversion command messages. 0x0001 ADC1 Control Register (ADC1_CR) Write/Read MPC5566 Microcontroller Reference Manual, Rev. 2 19-36 Freescale Semiconductor...
Page 840: Adcn Control Registers (Adc0_Cr And Adc1_Cr)
Note: Conversion commands sent to a disabled ADC are ignored by the ADC control hardware. Note: When the ADCn_EN status is changed from asserted to negated, the ADC clock does not stop until it reaches its low phase. 1–3 Reserved. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-37...
Page 841 Table 19-28. System Clock Divide Factor for ADC Clock System Clock ADCn_CLK_PS[0:4] Divide Factor 0b00000 0b00001 0b00010 0b00011 0b00100 0b00101 0b00110 0b00111 0b01000 0b01001 0b01010 0b01011 0b01100 0b01101 0b01110 0b01111 0b10000 0b10001 0b10010 MPC5566 Microcontroller Reference Manual, Rev. 2 19-38 Freescale Semiconductor...
Page 842: Adc Time Stamp Control Register (Adc_Tscr)
ADC0 writes to the same memory location as a write using a configuration command sent to ADC1. NOTE Simultaneous write accesses from ADC0 and ADC1 to ADC_TSCR are not allowed. Address: 0x0002 Access: R/W TBC_CLK_PS Reset Figure 19-20. ADC Time Stamp Control Register (ADC_TSCR) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-39...
Page 843: Adc Time Base Counter Registers (Adc_Tbcr)
ADC0 or to ADC1. A data write to ADC_TBCR using a configuration command sent to ADC0 writes the same memory location as a write using a configuration command sent to ADC1. MPC5566 Microcontroller Reference Manual, Rev. 2 19-40 Freescale Semiconductor...
Page 844 Section 19.4.5.4, “ADC Calibration Feature,” for details about the calibration scheme used in the eQADC. Address: 0x0004 Access: R/W GCC0 Reset GCC1 Reset Figure 19-22. ADCn Gain Calibration Constant Registers (ADCn_GCCR) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-41...
Page 845: Functional Description
CFIFOs by the host CPU or by the eDMA which responds to interrupt and eDMA requests generated by the eQADC. The eQADC supports software and MPC5566 Microcontroller Reference Manual, Rev. 2 19-42...
Page 846: Data Flow In The Eqadc
A result message is composed of an RFIFO header and an ADC Result. The FIFO control unit decodes the information contained in the RFIFO MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 847 SSI NOTES: External Device eQADC SSI n = 0, 1, 2, 3, 4, 5 CFIFO Header Logic ADC Command & Command Buffers Message Figure 19-24. Command Flow During eQADC Operation MPC5566 Microcontroller Reference Manual, Rev. 2 19-44 Freescale Semiconductor...
Page 848: Assumptions/Requirements Regarding The External Device
ADCs being command buffer 0 and 1). The external device decides to which external command buffer a command should go by decoding the upper bit (BN bit) of the ADC command - see Section , MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-45...
Page 849: Command Execution And Result Return
A result message is composed of an RFIFO header and an ADC result. The FIFO control unit decodes the information contained in the RFIFO header to determine the RFIFO to which the ADC result is sent. The ADC result field is always 16 bits. MPC5566 Microcontroller Reference Manual, Rev. 2 19-46 Freescale Semiconductor...
Page 850: Message Formats For On-Chip Adc Operation
Address: 0x0005 Access: R/W EOQ PAUSE Reserved MESSAGE_TAG (0b0) CFIFO Header ADC Command CHANNEL_NUMBER ADC_REG_ADDRESS Address Field Figure 19-26. Conversion Command Message Format for On-Chip ADC Operation MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-47...
Page 851 Buffer number. For internal commands, ADCs 1 and 0 can be internal or external depending on the EBI bit setting. 0 Message ADC 0. 1 Message ADC 1. Calibration. Indicates if the returning conversion result must be calibrated. 0 Do not calibrate conversion result. 1 Calibrate conversion result. MPC5566 Microcontroller Reference Manual, Rev. 2 19-48 Freescale Semiconductor...
Page 852 ADCs into the 16-bit format which is sent to the RFIFOs. Refer to Section , “ADC Result Format for On-Chip ADC Operation,” for details. 0 Right justified unsigned. 1 Right justified signed. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-49...
Page 853 Note: If both the pause and EOQ bits are asserted in the same command message, the respective flags are set, but the CFIFO status changes as if only the EOQ bit were asserted. MPC5566 Microcontroller Reference Manual, Rev. 2 19-50...
Page 854 R/W bit. EOQ PAUSE Reserved MESSAGE_TAG Reserved (0b0) (0b1) CFIFO Header ADC Command Reserved ADC_REG_ADDRESS ADC Address Figure 19-28. Read Configuration Command Message Format for On-Chip ADC Operation MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-51...
Page 855 Buffer number. Indicates to which buffer the message is sent. Buffers 1 and 0 can either be internal or external depending on the EBI bit setting. 0 Message buffer 0. 1 Message buffer 1. Read/write. An asserted R/W bit indicates a read configuration command. 0 Write 1 Read MPC5566 Microcontroller Reference Manual, Rev. 2 19-52 Freescale Semiconductor...
Page 856 When the CAL bit is negated, this 14-bit data is obtained by executing a 2-bit left-shift on the 12-bit data received from the ADC. When the CAL bit is asserted, MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 857 Sign extension. These two bits are always zero for FMT=0 because unsigned results are positive. SIGN_ EXT[0:1] 2–15 Conversion result. A digital value corresponding to the analog input voltage in a channel when the conversion CONVERSION command was initiated. _RESULT [0:13] MPC5566 Microcontroller Reference Manual, Rev. 2 19-54 Freescale Semiconductor...
Page 858: Message Formats For External Device Operation
FIFO control unit/external device to which the command and the external command buffer is sent. The remaining 25 bits can be anything decodable by the external device. Only the ADC command portion of a command message is transferred to the external device. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-55...
Page 859 It is 25 bits long and it is transferred together with the BN bit to the external device when the CFIFO is COMMAND triggered. Refer to Section , “Conversion Command Message Format for On-Chip ADC Operation,” for a [0:24] description of the command message used when interfacing with the on-chip ADCs. MPC5566 Microcontroller Reference Manual, Rev. 2 19-56 Freescale Semiconductor...
Page 860 The ADC_RESULT of any incoming message with a null message tag is [0:15] ignored. When the MESSAGE_TAG is for an RFIFO, the eQADC extracts the 16-bit ADC_RESULT from the raw message and stores it into the appropriate RFIFO. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-57...
Page 861 (0b1000). The eQADC does not store into an RFIFO any incoming message with a null message tag. CONTENTS OF EQADC_NMSFR REGISTER CONTENTS OF EQADC_NMSFR REGISTER Figure 19-33. Null Message Send Format for External Device Operation MPC5566 Microcontroller Reference Manual, Rev. 2 19-58 Freescale Semiconductor...
Page 862: Command/Result Queues
When a CFIFO is not full, the eQADC sets the corresponding CFFF bit in Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn).” If MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-59...
Page 863 (EQADC_FISRn),” is decremented by 1, and transfer next data pointer n is incremented by 1 (or wrapped around) to point to the next entry in the CFIFO. The transfer of entries bound for the on-chip MPC5566 Microcontroller Reference Manual, Rev. 2 19-60...
Page 864 CFIFO with 16 entries is shown for clarity of explanation, the actual hardware implementation has only four entries. In this example, CFIFOn with 16 entries is shown in sequence after pushing and transferring entries. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-61...
Page 865: Cfifo Prioritization And Command Transfer
• Its commands are bound for an internal command buffer that is not full, and it is the highest priority triggered CFIFO sending commands to that buffer. MPC5566 Microcontroller Reference Manual, Rev. 2 19-62 Freescale Semiconductor...
Page 866 BUSY fields of the incoming result messages from the external device (see Section , “Result Message Format for External Device Operation,” for details). MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-63...
Page 867 This occurs when the eQADC acknowledges that the status of a higher-priority CFIFO has changed to the TRIGGERED state and attempts to schedule that CFIFO MPC5566 Microcontroller Reference Manual, Rev. 2 19-64...
Page 868 CFIFO4 Command for EQADC SSI Usage Command CFIFO5 eQADC SSI Serial Link External Device External SSI Interface Device Command Buffer2 Command ADC2 Command Buffer3 Command ADC3 Figure 19-37. CFIFO Prioritization Logic MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-65...
Page 869: External Trigger From Etpu Or Emios Channels
CFIFO trigger mode. Only then, after a valid trigger event is detected, the eQADC accordingly changes the CFIFO status. Refer to Figure 19-38 for an example. MPC5566 Microcontroller Reference Manual, Rev. 2 19-66 Freescale Semiconductor...
Page 870: Cfifo Scan Trigger Modes
CFIFOs can be changed from any other mode to disabled at any time. No trigger event can initiate command transfers from a CFIFO which has its MODE field programmed to disabled. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 871: Single-Scan Mode
In single-scan mode, a single pass through a sequence of command messages in the user-defined command queue is performed. In single-scan software trigger mode, the CFIFO is triggered by an asserted single-scan status bit, EQADC_FISRn[SSS] (see Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 MPC5566 Microcontroller Reference Manual, Rev. 2 19-68 Freescale Semiconductor...
Page 872 The eQADC clears the SSS bit and stops transferring commands from a triggered CFIFO when an asserted EOQ bit is encountered or when CFIFO status changes from triggered due to the detection of a closed gate. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 873: Continuous-Scan Mode
CFIFO to detect such event. A trigger overrun happens when the CFIFO is already in a TRIGGERED state and a new edge trigger event is detected. MPC5566 Microcontroller Reference Manual, Rev. 2 19-70 Freescale Semiconductor...
Page 874: Cfifo Scan Trigger Mode Start/Stop Summary
SSS bit is asserted. from the CFIFO when CFIFO status changes from triggered due to the detection of a closed gate. Continuous CFIFO starts None. Scan Software automatically after being configured into this mode. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-71...
Page 875: Cfifo And Trigger Status
(EQADC_CFSSRn).” The last CFIFO to transfer a command to a specific external command buffer can be identified by reading the EQADC_CFSSRn[LCFTSSI] and EQADC_CFSSRn[ENI] fields (see Section 19.3.2.10, “eQADC CFIFO Status Snapshot Registers 0–2 (EQADC_CFSSRn).” MPC5566 Microcontroller Reference Manual, Rev. 2 19-72 Freescale Semiconductor...
Page 876 • No trigger occurred. TRIGGER (0b10) TRIGGERED • Appropriate edge or level trigger occurred, OR (0b11) • CFIFO mode is programmed to single-scan software trigger mode and SSS bit is asserted. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-73...
Page 877: Command Queue Completion Status
The command with a EOQ bit asserted is valid and is transferred. When EQADC_CFCRn[EOQIE] (refer Section 19.3.2.6, “eQADC CFIFO Control Registers 0–5 (EQADC_CFCRn)”) and EQADC_FISRn[EOQF] are asserted, the eQADC generates an end of queue interrupt request. MPC5566 Microcontroller Reference Manual, Rev. 2 19-74 Freescale Semiconductor...
Page 878: Pause Status
In software or level trigger mode, when the eQADC completes the transfer of an entry from CFIFOn with an asserted pause bit, PFn is not set and the command transfers continues without pausing. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-75...
Page 879: Trigger Overrun Status
ADC command buffer, the buffer is only fed with commands from that sequence without ever becoming empty. A command sequence starts when: • A CFIFO in TRIGGERED state transfers its first command to an on-chip ADC. MPC5566 Microcontroller Reference Manual, Rev. 2 19-76 Freescale Semiconductor...
Page 880 CFn_ADCa_CMDn – Command n in CFIFOn bound for ADCa CF5_ADC2_CM5 (ADC3 and ADC4 are external devices associated with external CF5_ADC1_CM6(EOQ=1) command buffers 2 and 3). Example 3 Figure 19-41. Command Sequence Examples MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-77...
Page 881 2) Execution of a command on the external device takes longer than the time to complete two serial transmissions. Figure 19-42. External Command Buffer Status Detection at Command Sequence Transfer Start MPC5566 Microcontroller Reference Manual, Rev. 2 19-78 Freescale Semiconductor...
Page 882 When the eQADC enters debug or stop mode while a command sequence is executing, the NCF asserts if an empty external command buffer is detected after debug or stop mode exits. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-79...
Page 883 CFIFO5 becomes non-coherent. CF5_ADC1_CM3 TNXTPTR – Transfer Next Data Pointer. CFx_ADCa_CMn – Command n in CFIFOx bound for ADCa. Figure 19-43. Non-Coherency Event When Different CFIFOs Use the Same Buffer MPC5566 Microcontroller Reference Manual, Rev. 2 19-80 Freescale Semiconductor...
Page 884 TNXTPTR – Transfer Next Data Pointer. CFx_ADCa_CMn – Command n in CFIFOx bound for external command buffer a. Figure 19-44. Non-Coherency Event When Different CFIFOs Are Using Different External Command Buffers MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-81...
Page 885: Result Fifos
RFIFO message to be retrieved from the RFIFO when reading eQADC_RFPR. The receive next data pointer points to the next available RFIFO location for storing the next incoming MPC5566 Microcontroller Reference Manual, Rev. 2 19-82...
Page 886 When the eQADC RFIFO pop register n is read and RFIFOn is empty, eQADC does not decrement the counter value and the pop next data pointer n is not updated. The read value is undefined. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 887 RFIFO with 16 entries is shown for clarity of explanation, the actual hardware implementation has only four entries. In this example, RFIFOn with 16 entries is shown in sequence after popping or receiving entries. MPC5566 Microcontroller Reference Manual, Rev. 2 19-84 Freescale Semiconductor...
Page 888: Distributing Result Data Into Rfifos
Stores the 16-bit data into the appropriate RFIFO if the MESSAGE_TAG indicates a valid RFIFO number; or • Ignores the data in case of a null or “reserved for customer use” MESSAGE_TAG MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-85...
Page 889: On-Chip Adc Configuration And Control
The clock input to the ADCs is defined by setting the ADC0_CR[ADC0_CLK_PS] and ADC1_CR[ADC1_CLK_PS] fields. Refer to Section 19.3.3.1, “ADCn Control Registers (ADC0_CR and ADC1_CR).” The ADC0/1_CLK_PS field selects the clock divide factor by which the system clock is MPC5566 Microcontroller Reference Manual, Rev. 2 19-86 Freescale Semiconductor...
Page 890 ADC clock frequency higher than the maximum one supported by the ADC. ADC clock frequency must not exceed 12 Mhz. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 891 0b01100 4.62 0b01101 4.29 0b01110 0b01111 3.75 0b10000 3.53 0b10001 3.33 0b10010 3.16 0b10011 0b10100 2.86 0b10101 2.73 0b10110 2.61 0b10111 0b11000 0b11001 2.31 0b11010 2.22 0b11011 2.14 0b11100 2.07 0b11101 MPC5566 Microcontroller Reference Manual, Rev. 2 19-88 Freescale Semiconductor...
Page 892: Time Stamp Feature
CAL_RES is the calibrated result corresponding the input voltage V • GCC is the gain calibration constant. • RAW_RES is the raw, uncalibrated result corresponding to an specific input voltage V • OCC is the offset calibration constant. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-89...
Page 893: Mac Unit And Operand Data Format
CAL_RES output is the calibrated result, and it is a 14-bit unsigned value. CAL_RES is truncated to 0x3FFF, in case of a overflow, and to 0x0000, in case of an underflow. MPC5566 Microcontroller Reference Manual, Rev. 2 19-90 Freescale Semiconductor...
Page 894: Adc Control Logic Overview And Command Execution
The FIFO control unit decodes these bits and sends the ADC command to the proper ADC. Other blocks of logic are the result format and calibration submodule, the time stamp logic, and the MUX control logic. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 895 The second advantage of pipelining conversion commands is to provide equal conversion intervals even though the sample time increases on second and subsequent conversions. Refer to Figure 19-52. This is important for any digital signal process application. MPC5566 Microcontroller Reference Manual, Rev. 2 19-92 Freescale Semiconductor...
Page 896 Result Format ADC0_Result0 Stamp Logic ADC1_Result1 Time Stamp0 Calibration Time Stamp1 Submodule TBC_CLK_PS Configuration Register Fields NOTE: n = 0, 1, 2, 3, 4, 5 Figure 19-51. On-Chip ADC Control Scheme MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-93...
Page 897: Internal/External Multiplexing
ADC. The differential conversions can only be initiated on four channels: DAN0, DAN1, DAN2, and DAN3. Refer to Table 19-51 Figure 19-52 for the channel numbers used to select differential conversions. MPC5566 Microcontroller Reference Manual, Rev. 2 19-94 Freescale Semiconductor...
Page 898 ADCn_EMUX bit asserted can access at most 33 single-ended and 32 externally multiplexed channels. Refer to Section 19.4.6.2, “External Multiplexing,” for a detailed explanation about how external multiplexing can be achieved. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-95...
Page 899: External Multiplexing
ADC0/1_EMUX bit in either ADC0_CR or ADC1_CR depending on which ADC performs the conversion. Figure 19-52 shows the channel number assignments for the multiplexed mode. Only one ADC can have its ADC0/1_EMUX bit asserted at a time. MPC5566 Microcontroller Reference Manual, Rev. 2 19-96 Freescale Semiconductor...
Page 900 (ANW, ANX, ANY, and ANZ) by interpreting the CHANNEL_NUMBER field. As a result, up to 32 externally multiplexed channels appear to the conversion queues as directly connected signals. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-97...
Page 901: Eqadc Edma/Interrupt Request
(EQADC_IDCRn),” and the interrupt flag bits are described in Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn).” Table 19-54 depicts all interrupts and eDMA requests generated by the eQADC. MPC5566 Microcontroller Reference Manual, Rev. 2 19-98 Freescale Semiconductor...
Page 902 Writing 1 to the CFFFn bit is not allowed while CFDS = 1. CFFFn = 1 For details refer to Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn),” and Section 19.3.2.7, “eQADC Interrupt and eDMA Control Registers 0–5 (EQADC_IDCRn).” MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-99...
Page 903 End of Queue Interrupt Request EOQFn TORIEn Trigger Overrun Interrupt Request TORFn CFUIEn CFIFO Underflow Interrupt Request CFUFn RFOIEn RFIFO Overflow Interrupt Request RFOFn Combined Interrupt Request Figure 19-54. eQADC eDMA and Interrupt Requests MPC5566 Microcontroller Reference Manual, Rev. 2 19-100 Freescale Semiconductor...
Page 904: Eqadc Synchronous Serial Interface (Ssi) Submodule
26-bit receive shift register in the slave are linked by the SDO pin. In a similar way, the 26-bit transmit shift register in the slave and 26-bit receive shift register in the master are linked by the SDI pin. Refer to MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 905: Eqadc Ssi Data Transmission Protocol
SDS was detected by the slave on the preceding FCK negative edge. This is an important requisite since the SDS and the FCK are not MPC5566 Microcontroller Reference Manual, Rev. 2 19-102...
Page 906: Abort Feature
(EQADC_SSICR)”) selects the system clock divide factor as in Table 19-21. SystemClockFrequency MHz BaudClockFrequency --------------------------------------------------------------------------------------- - SystemClockDivideFactor Maximum FCK frequency is highly dependable on track delays, master pad delays, and slave pad delays. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-103...
Page 907 23 24 25 26 23 24 25 Slave Sample Input NOTE: = Minimum t is programmable and defined in Section 18.3.2.12, ‘eQADC SSI Control Register (EQADC_SSICR).’ Figure 19-57. Synchronous Serial Interface Protocol Timing MPC5566 Microcontroller Reference Manual, Rev. 2 19-104 Freescale Semiconductor...
Page 908 Slave drives msb bit again due to detection of a negated SDS on the negative edge of FCK. Figure 19-58. Slave Driving the msb and Consecutive Bits in a Data Transmission MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-105...
Page 909: Analog Submodule
The digital module also saves each successive sample and adds them according to the RSD algorithm at the end of the entire conversion cycle. MPC5566 Microcontroller Reference Manual, Rev. 2 19-106 Freescale Semiconductor...
Page 910: Rsd Overview
For the 12-bit ADC, the input signal is sampled during the input phase, and after each of the 12 passes through the RSD stage. Thus, 13 total a and b values are collected. Upon collecting all these MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 911: Rsd Adder
Every 900 μs Fast Current sensing of PWM hardware-triggered controlled actuators queue Fast repetitive Every 2 ms Throttle position time-based queue Software-triggered Every 3.9 ms Command triggered by queue software strategy MPC5566 Microcontroller Reference Manual, Rev. 2 19-108 Freescale Semiconductor...
Page 912: Initialization Of On-Chip Adcs And An External Device
8. Because CFIFO0 is in single-scan software mode and it is also the highest priority CFIFO, the eQADC starts to transfer configuration commands to the on-chip ADCs and to the external device. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 913: Configuring Eqadc For Applications
At the end of the command queue, the “EOQ” bit is asserted as shown in Table 19-57. c) Results are returned to RFIFO3 as specified in the MESSAGE_TAG field of commands. 2. Reserve memory space for storing results. MPC5566 Microcontroller Reference Manual, Rev. 2 19-110 Freescale Semiconductor...
Page 914 2. For receiving, set the source address of the eDMA TCDn to point to EQADC_RFPR3. Refer to Section 19.3.2.5, “eQADC Result FIFO Pop Registers 0–5 (EQADC_RFPRn).” Set the destination address of the eDMA to point to the starting address of result queue 1. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-111...
Page 915: Eqadc/Edma Controller Interface
CFIFO Push Register One command transfer Command 3 per DMA request • • eDMA_TCDn • • • • Source Address Command n-1 Command n Destination Address Figure 19-65. Command Queue/CFIFO Interface MPC5566 Microcontroller Reference Manual, Rev. 2 19-112 Freescale Semiconductor...
Page 916: Receive Queue/Rfifo Transfers
Result 2 RFIFO Pop Register One result transfer Result 3 per DMA request • • • • • Source Address • Result n-1 Destination Address Result n Figure 19-66. Receive Queue/RFIFO Interface MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-113...
Page 917: Sending Immediate Command Setup Example
Section 19.4.3.5.1, “Disabled Mode,” for a description of what happens when MODEn is changed to disabled. b) Poll EQADC_CFSR[CFSn] until it becomes IDLE (see Section 19.3.2.11, “eQADC CFIFO Status Register (EQADC_CFSR)”). MPC5566 Microcontroller Reference Manual, Rev. 2 19-114 Freescale Semiconductor...
Page 918: Command Queue And Result Queue Usage
0 command was sent to result queue 1. This happens because the system can be configured so that several command queues can have results sent to a single result queue. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-115...
Page 919: Adc Result Calibration
This allows for calculations of more representative calibration constants. The eQADC provides these voltages via channel numbers 43 and 44. MPC5566 Microcontroller Reference Manual, Rev. 2 19-116...
Page 920: Mac Configuration Procedure
4. Reformat GCC and OCC to the proper data formats as specified in Section 19.4.5.4.2, “MAC Unit and Operand Data Format.” GCC is an unsigned 15-bit fixed point value and OCC is a signed 14-bit value. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-117...
Page 921: Example Calculation Of Calibration Constants
See MAC output equation in Section 19.4.5.4, “ADC Calibration Feature.” The maximum absolute quantization error is reduced by half leading to an increase in accuracy. 1. This calculation is rounded down due to binary approximation. MPC5566 Microcontroller Reference Manual, Rev. 2 19-118 Freescale Semiconductor...
Page 922: Eqadc Versus Qadc
QADC. Digital control logic for analog Analog-to-digital converter device Trigger & External queue control Command queues Result queues triggers logic Interrupt request Figure 19-69. QADC Overview MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-119...
Page 923 FIFO instead of queue. These register names, register contents, and signals are functionally equivalent to the queue counterparts in the QADC. Table 19-59 lists how the eQADC register, register contents, and signals are related to QADC. MPC5566 Microcontroller Reference Manual, Rev. 2 19-120 Freescale Semiconductor...
Page 924 Write to the eQADC SSI registers. Queue Execution Require software or external trigger Require software or external trigger events to start queue execution. events to start command transfers from a CFIFO. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 19-121...
Page 925 Enhanced Queued Analog-to-Digital Converter (eQADC) MPC5566 Microcontroller Reference Manual, Rev. 2 19-122 Freescale Semiconductor...
Page 926: Introduction
A, B, C, and D, and others implement only B, C, and D, for example. The “x” appended to signal names signifies the module to which the signal applies. Thus PCSx[0] specifies that the PCS signal applies to module A, B, and so on. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-1...
Page 927: Block Diagram
Deserial serial interface (DSI) configuration where the DSPI serializes eTPU and eMIOS output channels and deserializes the received data by placing the data on the eTPU and eMIOS input channels and as inputs to the external interrupt request submodule of the SIU. MPC5566 Microcontroller Reference Manual, Rev. 2 20-2 Freescale Semiconductor...
Page 928: Features
— Programmable serial frame size of 4 to 16 bits, expandable with software control — Continuously held chip select capability • Six peripheral chip selects, expandable to 64 with external demultiplexer • Deglitching support for up to 32 peripheral chip selects with external demultiplexer MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-3...
Page 929 – Continuous – Edge-sensitive hardware trigger – Change in data • Support for parallel and serial chaining of DSPI modules • Pin serialization/deserialization with interleaved SPI frames for control and diagnostics MPC5566 Microcontroller Reference Manual, Rev. 2 20-4 Freescale Semiconductor...
Page 930: Modes Of Operation
FRZ bit is cleared, the DSPI behavior is unaffected and remains dictated by the module-specific mode and configuration of the DSPI. For more information, see Section 20.4.1.4, “Debug Mode.” MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-5...
Page 931: External Signal Description
Section 6.3.1.12, “Pad Configuration Registers (SIU_PCR),” for more information. 20.2.2.2 Peripheral Chip Selects 1–3 (PCSx[1:3]) PCSx[1:3] are peripheral chip select output signals in master mode. In slave mode these signals are not used. MPC5566 Microcontroller Reference Manual, Rev. 2 20-6 Freescale Semiconductor...
Page 932: Peripheral Chip Select 4 / Master Trigger (Pcsx[4]_Mtrig)
0xFFF9_8000 (DSPI C) 0xFFF9_C000 (DSPI D) Base + 0x0004 — Reserved — Base + 0x0008 DSPIx_TCR DSPI transfer count register Base + 0x000C DSPIx_CTAR0 DSPI clock and transfer attributes register 0 MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-7...
Page 933: Register Descriptions
The HALT and MDIS bits in the DSPIx_MCR are the only bit values software can change while the DSPI is running. MPC5566 Microcontroller Reference Manual, Rev. 2 20-8...
Page 934 Invalid value Freeze. Enables the DSPI transfers to be stopped on the next frame boundary when the device enters debug mode. 0 Do not halt serial transfers 1 Halt serial transfers MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-9...
Page 935 Disable receive FIFO. Enables and disables the RX FIFO. When the RX FIFO is disabled, the receive part of DIS_RXF the DSPI operates as a simplified double-buffered SPI. See Section 20.4.3.3, “FIFO Disable Operation details.” 0 RX FIFO is enabled 1 RX FIFO is disabled MPC5566 Microcontroller Reference Manual, Rev. 2 20-10 Freescale Semiconductor...
Page 936: Dspi Transfer Count Register (Dspix_Tcr)
The DSPIx_TCR contains a counter that indicates the number of SPI transfers made. The transfer counter is intended to assist in queue management. The user must not write to the DSPIx_TCR while the DSPI is running. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-11...
Page 937: Dspi Clock And Transfer Attributes Registers 0–7 (Dspix_Ctarn)
In slave mode, a subset of the bit fields in the DSPIx_CTAR0 and DSPIx_CTAR1 registers are used to set the slave transfer attributes. See the individual bit descriptions for details on which bits are used in slave modes. MPC5566 Microcontroller Reference Manual, Rev. 2 20-12 Freescale Semiconductor...
Page 938 Base + 0x001C (DSPIx_CTAR4) Base + 0x0020 (DSPIx_CTAR5) Base + 0x0024 (DSPIx_CTAR6) Base + 0x0028 (DSPIx_CTAR7) FMSZ CPOL CPHA PCSSCK PASC Reset CSSCK Reset Figure 20-5. DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-13...
Page 939 The following table lists the frame sizes. [0:3] FMSZ Frame Size FMSZ Frame Size 0000 Invalid value 1000 0001 Invalid value 1001 0010 Invalid value 1010 0011 1011 0100 1100 0101 1101 0110 1110 0111 1111 MPC5566 Microcontroller Reference Manual, Rev. 2 20-14 Freescale Semiconductor...
Page 940 PCSx. Use in master mode only. The following table lists the prescaler values. The description for bitfield ASC in [0:1] Table 20-5 details how to compute the after SCKx delay. PASC After SCKx Delay Value Prescaler Value MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-15...
Page 941 The baud rate prescaler values are listed in the following table. The description for PBR in Section 20.4.6.1, “Baud Rate Generator” details how to compute the baud rate. Baud Rate Value Prescaler Value MPC5566 Microcontroller Reference Manual, Rev. 2 20-16 Freescale Semiconductor...
Page 942 The after SCKx delay is a multiple of the system clock period, and it is computed using the following equation: × × ----------- PASC Prescaler value ASC Scaler value Note: See Section 20.4.6.3, “After SCK Delay (tASC),” for more details. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-17...
Page 943 The delay after transfer is a multiple of the system clock period. It is computed using the following equation: × × ----------- PDT Prescaler value DT Scaler value Note: See Section 20.4.6.4, “Delay after Transfer (tDT),” for more details MPC5566 Microcontroller Reference Manual, Rev. 2 20-18 Freescale Semiconductor...
Page 944: Dspi Status Register (Dspix_Sr)
DSPIx_SR by writing a 1 to clear it (w1c). Writing a 0 to a flag bit has no effect. Address: Base + 0x002C Access: R/W R TCF TXRXS EOQF TFUF TFFF RFOF RFDF W w1c Reset TXCTR TXNXTPTR RXCTR POPNXTPTR Reset Figure 20-6. DSPI Status Register (DSPIx_SR) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-19...
Page 945 RX FIFO and shift register are full and a transfer is initiated. The bit is cleared by writing 1 to it. 0 RX FIFO overflow has not occurred 1 RX FIFO overflow has occurred Reserved MPC5566 Microcontroller Reference Manual, Rev. 2 20-20 Freescale Semiconductor...
Page 946 Do not write to the DSPIx_RSER while the DSPI is running. Address: Base + 0x0030 Access: R/W TCF_ EOQF TFUF_ TFFF_ TFFF_ RFOF RFDF RFDF_ DIRS DIRS Reset Reset Figure 20-7. DSPI DMA / Interrupt Request Select and Enable Register (DSPIx_RSER) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-21...
Page 947 RFDF_RE RFDF_DIRS bit selects between generating an interrupt request or a DMA request. 0 RFDF interrupt requests or DMA requests are disabled 1 RFDF interrupt requests or DMA requests are enabled MPC5566 Microcontroller Reference Manual, Rev. 2 20-22 Freescale Semiconductor...
Page 948: Dspi Push Tx Fifo Register (Dspix_Pushr)
TXDATA is used in master and slave modes. Address: Base + 0x0034 Access: R/W CONT CTAS PCS5 PCS4 PCS3 PCS2 PCS1 PCS0 Reset TXDATA Reset Figure 20-8. DSPI PUSH TX FIFO Register (DSPIx_PUSHR) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-23...
Page 949 0 Do not clear SPI_TCNT field in the DSPIx_TCR 1 Clear SPI_TCNT field in the DSPIx_TCR Note: Use in SPI master mode only. 6–7 Reserved 8–9 Reserved, but implemented. These bits are writable, but have no effect. MPC5566 Microcontroller Reference Manual, Rev. 2 20-24 Freescale Semiconductor...
Page 950: Dspi Pop Rx Fifo Register (Dspix_Popr)
FIFO. Therefore, read DSPIx_POPR only when you need the data. For compatibility, configure the TLB (MMU table) entry for DSPIx_POPR as guarded. Address: Base + 0x0038 Access: R/O Reset RXDATA Reset Figure 20-9. DSPI POP RX FIFO Register (DSPIx_POPR) MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-25...
Page 951: Dspi Transmit Fifo Registers 0–3 (Dspix_Txfrn)
Transmit command. Contains the command that sets the transfer attributes for the SPI data. See Section 20.3.2.6, TXCMD “DSPI PUSH TX FIFO Register (DSPIx_PUSHR),” for details on the command field. [0:15] 16–31 Transmit data. Contains the SPI data to be shifted out. TXDATA [0:15] MPC5566 Microcontroller Reference Manual, Rev. 2 20-26 Freescale Semiconductor...
Page 952: Dspi Receive Fifo Registers 0–3 (Dspix_Rxfrn)
The following table describes the field in the DSPI receive FIFO register: Table 20-11. DSPIx_RXFRn Field Description Field Description 0–15 Reserved, must be cleared. 16–31 Receive data. Contains the received SPI data. RXDATA [15:0] MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-27...
Page 953: Dspi Dsi Configuration Register (Dspix_Dsicr)
Trigger polarity. Selects the active edge of the internal hardware trigger input signal (ht). The bit selects which TPOL edge initiates a transfer in the DSI configuration. See Section 20.4.4.5, “DSI Transfer Initiation Control,” for more information. 0 Falling-edge initiates a transfer 1 Rising-edge initiates a transfer MPC5566 Microcontroller Reference Manual, Rev. 2 20-28 Freescale Semiconductor...
Page 954 DSI peripheral chip select n. The DPCS bits select which of the PCSx signals to assert during a DSI transfer. DPCSx The DPCS bits assert and negate the PCSx signals in DSI master mode only. 0 Negate PCSx 1 Assert PCSx MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-29...
Page 955: Dspi Dsi Serialization Data Register (Dspix_Sdr)
Serialized data. The SER_DATA field contains the signal states of the parallel input signals. SER_DATA [15:0] maps SER_ to DSPI serialization inputs IN[15:0]. See Section 20.4.4.6, “DSPI Connections to eTPUA, eTPUB, eMIOS and SIU.” DATA [15:0] MPC5566 Microcontroller Reference Manual, Rev. 2 20-30 Freescale Semiconductor...
Page 956: Dspi Dsi Alternate Serialization Data Register (Dspix_Asdr)
The following table describes the field in the DSPI deserial serial interface alternate serialization data register: Table 20-14. DSPIx_ASDR Field Description Field Description 0–15 Reserved 16–31 Alternate serialized data. The ASER_DATA field holds the alternate data to be serialized. ASER_ DATA [0:15] MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-31...
Page 957: Dspi Dsi Transmit Comparison Register (Dspix_Compr)
The following table describes the field in the DSPI deserial serial interface transmit comparison register: Table 20-15. DSPIx_COMPR Field Description Field Description 0–15 Reserved 16–31 Compare data. The COMP_DATA field holds the last serialized DSI data. COMP_ DATA [0:15] MPC5566 Microcontroller Reference Manual, Rev. 2 20-32 Freescale Semiconductor...
Page 958: Dspi Dsi Deserialization Data Register (Dspix_Ddr)
DSI frames with SPI frames, giving priority to SPI frames. The DCONF field in the DSPIx_MCR register determines the DSPI configuration. See Table 20-3 for the DSPI configuration values. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-33...
Page 959: Modes Of Operation
The module-specific modes are determined by bits in the DSPIx_MCR. Debug mode is a mode that the entire device can enter in parallel with the DSPI being configured in one of its module-specific modes. MPC5566 Microcontroller Reference Manual, Rev. 2 20-34...
Page 960: Master Mode
DSPI is stopped while in module disable mode. The DSPI enters the module disable mode when the MDIS bit in DSPIx_MCR is set. Section 20.4.10, “Power Saving Features,” for more details on the module disable mode. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-35...
Page 961: Debug Mode
The DSPI stops (transitions from RUNNING to STOPPED) after the current frame for any one of the following conditions: • EOQF bit is set • Debug mode is selected and the FRZ bit is set • HALT bit is set MPC5566 Microcontroller Reference Manual, Rev. 2 20-36 Freescale Semiconductor...
Page 962: Serial Peripheral Interface (Spi) Configuration
Certain transfer attributes such as clock polarity, clock phase and frame size must be set for successful communication with an SPI master. The SPI slave mode transfer attributes are set in the DSPIx_CTAR0. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-37...
Page 963: Fifo Disable Operation
DSPIx_PUSHR is complete or alternatively by host software writing a 1 to the TFFF in the DSPIx_SR. The TFFF can generate a DMA request or an interrupt request. Section 20.4.9.2, “Transmit FIFO Fill Interrupt or DMA Request (TFFF),” for details. MPC5566 Microcontroller Reference Manual, Rev. 2 20-38 Freescale Semiconductor...
Page 964: Draining The Tx Fifo
If the ROOE bit is set, the incoming data is put in the shift register. If the ROOE bit is cleared, the incoming data is ignored. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 965: Draining The Rx Fifo
The four transfer initiation conditions are described in Section 20.4.4.5, “DSI Transfer Initiation Control.” Transfer attributes are set during initialization. The DSICTAS field in the DSPIx_DSICR determines which of the DSPIx_CTARs controls the transfer attributes. MPC5566 Microcontroller Reference Manual, Rev. 2 20-40 Freescale Semiconductor...
Page 966: Dsi Slave Mode
TXSS Clock SCKx logic Shift register Parallel DSI serialization inputs data register SOUTx 0 1 • • • • • 15 Control logic PCSx Figure 20-19. DSI Serialization Diagram MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-41...
Page 967: Dsi Deserialization
DSPI and the external device. The baud rate is set in the DSPIx_CTAR selected by the DSICTAS field in the DSPIx_DSICR. A new DSI frame shifts out when the previous transfer cycle has completed and the delay after transfer (t ) has elapsed. MPC5566 Microcontroller Reference Manual, Rev. 2 20-42 Freescale Semiconductor...
Page 968: Change In Data Control
Table 20-19 lists the DSPI A connections. Table 20-19. DSPI A Connectivity Table DSPI A DSPI A Connected to: Connected to: IN[n] OUT[n] eTPUB Output Channel 15 eTPUB Output Channel 14 MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-43...
Page 969: Dspi B Connectivity
CH 29 IN 8 • • • • • • OUT 14 CH 13 CH 24 IN 13 OUT 15 CH 12 Figure 20-23. eMIOS, eTPUA and DSPI B Connectivity MPC5566 Microcontroller Reference Manual, Rev. 2 20-44 Freescale Semiconductor...
Page 970: Dspi C Connectivity
CH 0 IN 4 • • • • • • • • • • • • OUT 15 IN2 IRQ[14] CH 11 IN 15 Figure 20-24. eTPUA and DSPI C Connectivity MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-45...
Page 971: Dspi D Connectivity
CH 16 IN 5 eMIOS CH 29 IN 10 OUT 14 CH 15 • • • • • • OUT 15 CH 14 CH 24 IN 15 Figure 20-25. DSPI D Connectivity MPC5566 Microcontroller Reference Manual, Rev. 2 20-46 Freescale Semiconductor...
Page 972: Multiple Transfer Operation (Mto)
When a DSPI slave detects a trigger signal on its ht input, the slave generates a trigger signal on the MTRIG output. The SIU_DISR must be configured to use serial or parallel chaining. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-47...
Page 973: Internal Muxing And Siu Support For Serial And Parallel Chaining
(ht) input can be the MTRIG signal from any of the other DSPIs. The DSPI input select register (SIU_DSR) selects the source for each DSPI SINx, SSx, SCKx, and ht signal individually. MPC5566 Microcontroller Reference Manual, Rev. 2 20-48...
Page 974: Parallel Chaining
The MTOCNT field in the DSPIx_DSICR must be written with the number of bits to be transferred. In parallel chaining the number written to MTOCNT must match the FMSZ field in the selected DSPIx_CTAR. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-49...
Page 975: Serial Chaining
DSI frames, as long as each DSPI transfers a minimum of 4 bits and a maximum of 16 bits and the total size of the concatenated frame is less than or equal to64 bits long. MPC5566 Microcontroller Reference Manual, Rev. 2 20-50...
Page 976: Combined Serial Interface (Csi) Configuration
SPI frames are determined by the DSPIx_CTAR selected by the CTAS field in the SPI command halfword. The transfer attributes for the DSI frames are determined by the DSPIx_CTAR selected by the DSICTAS field in the DSPIx_DSICR. Figure 20-30 shows the CSI serialization logic. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-51...
Page 977: Csi Deserialization
Slave bus interface Control logic RX FIFO Transfer Shift register priority logic 0 1 • • • • • 15 Parallel DSI deserialization outputs data register (P_OUT) Figure 20-31. CSI Deserialization Diagram MPC5566 Microcontroller Reference Manual, Rev. 2 20-52 Freescale Semiconductor...
Page 978: Dspi Baud Rate And Clock Delay Generation
PCS to SCK delay. Table 20-24. PCS to SCK Delay Computation Example Prescaler Scaler PCSSCK CSSCK PCS to SCK Delay Value Value 0.96 μs 0b01 0b0100 100 MHz MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-53...
Page 979: Peripheral Chip Select Strobe Enable (Pcss)
When the DSPI is in master mode and PCSSE bit is set in the DSPIx_MCR, PCSS provides a signal for an external demultiplexer to decode the PCSx[0:4] signals into as many as 32 glitch-free PCSx signals. MPC5566 Microcontroller Reference Manual, Rev. 2 20-54 Freescale Semiconductor...
Page 980: Transfer Formats
(DSPIx_CTARn) select the polarity and phase of the serial clock, SCKx. The polarity bit selects the idle state of the SCKx. The clock phase bit selects if the data on SOUTx is valid before or on the first SCKx edge. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-55...
Page 981 Format Enabled (MTFE = 1) with Classic SPI Transfer Format Set (CPHA = 1) for SPI and DSI.” In the SPI and DSI configurations, the DSPI provides the option of keeping the PCS signals asserted between frames. See Section 20.4.7.5, “Continuous Selection Format” for details. MPC5566 Microcontroller Reference Manual, Rev. 2 20-56 Freescale Semiconductor...
Page 982: Classic Spi Transfer Format (Cpha = 0)
For the CPHA = 0 condition of the slave, TCF is set and the RXCTR counter is updated at the last serial clock edge of the frame (edge 16) of Figure 20-34. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-57...
Page 983: Classic Spi Transfer Format (Cpha = 1)
For CPHA = 1 the master EOQF and TCF and slave TCF are set at the last serial clock edge (edge 16) of Figure 20-35. For CPHA = 1 the master and slave RXCTR counters are updated on the same clock edge. MPC5566 Microcontroller Reference Manual, Rev. 2 20-58 Freescale Semiconductor...
Page 984: Modified Transfer Format Enabled (Mtfe = 1) With Classic Spi Transfer Format Cleared (Cpha = 0) For Spi And Dsi
SMPL_PT bit field. The master sample point can be delayed by one or two system clock cycles. Table 20-29. Delayed Master Sample Point Number of System Clock Cycles between SMPL_PT Odd-numbered Edge of SCK and Sampling of SIN Invalid value MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-59...
Page 985: Modified Transfer Format Enabled (Mtfe = 1) With Classic Spi Transfer Format Set (Cpha = 1) For Spi And Dsi
The SCK-to-PCS delay must be greater or equal to half of the SCK period. NOTE For the modified transfer format to operate correctly, you must thoroughly analyze the SPI link timing budget. MPC5566 Microcontroller Reference Manual, Rev. 2 20-60 Freescale Semiconductor...
Page 986: Continuous Selection Format
When the CONT bit = 0, the DSPI drives the asserted chip select signals to their idle states in between frames. The idle states of the chip select signals are selected by the PCSIS field in the DSPIx_MCR. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 987 When the CONT bit = 1 and the PCS signals for the next transfer are different from the present transfer, the PCS signals behave as if the CONT bit was not set. MPC5566 Microcontroller Reference Manual, Rev. 2 20-62 Freescale Semiconductor...
Page 988: Clock Polarity Switching Between Dspi Transfers
The device is designed to use the same baud rate for all transfers made while using the continuous SCK. Switching clock polarity between frames while using continuous SCK can cause errors in the transfer. Continuous SCK operation is not guaranteed if the DSPI is put into module disable mode. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-63...
Page 989 SCK format with continuous selection enabled. (CPOL = 0) (CPOL = 1) Master SOUT Master SIN Transfer 1 Transfer 2 Figure 20-42. Continuous SCK Timing Diagram (CONT=1) MPC5566 Microcontroller Reference Manual, Rev. 2 20-64 Freescale Semiconductor...
Page 990: Interrupts And Dma Requests
TCF_RE bit is set in the DSPIx_RSER. See the TCF bit description in Section 20.3.2.4, “DSPI Status Register (DSPIx_SR).” See Figure 20-34 Figure 20-35 that illustrate when TCF is set. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-65...
Page 991: Transmit Fifo Underflow Interrupt Request (Tfuf)
Changes to the DIS_TXF and DIS_RXF fields of the DSPIx_MCR does not have any affect in the module disable mode. In the module disable mode, all status bits and register flags MPC5566 Microcontroller Reference Manual, Rev. 2 20-66...
Page 992: Slave Interface Signal Gating
8. Enable the DMA channel by setting the DMA enable request bit for the DMA channel assigned to the DSPI TX and RX FIFOs. 9. Enable serial transmission and serial reception of data by clearing the EOQF bit. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-67...
Page 993: Baud Rate Settings
4.88 kHz 3.49 kHz 4096 6.10 kHz 4.07 kHz 2.44 kHz 1.74 kHz 8192 3.05 kHz 2.04 kHz 1.22 kHz 872 Hz 16384 1.53 kHz 1.02 kHz 610 Hz 436 Hz 32768 MPC5566 Microcontroller Reference Manual, Rev. 2 20-68 Freescale Semiconductor...
Page 994: Delay Settings
DSPIx_CTARs to match the default cases for the possible combinations of the MPC5xx family control bits in its command RAM. The defaults for the MPC5xx family are based on a system clock of 40 MHz. MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-69...
Page 995: Calculation Of Fifo Pointer Addresses
Section 20.4.3.5, “Using the RX FIFO Buffering Mechanism,” for details on the FIFO operation. The TX FIFO is chosen for the illustration, but the concepts carry over to the RX FIFO. MPC5566 Microcontroller Reference Manual, Rev. 2 20-70 Freescale Semiconductor...
Page 996: Entry In The Tx Fifo
[(RXCTR + POPNXTPTR - 1) modulo RXFIFO depth] where: RXFIFO base = base address of receive FIFO RXCTR = receive FIFO counter POPNXTPTR = pop next pointer RX FIFO depth = receive FIFO depth, implementation specific MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 20-71...
Page 997 Deserial Serial Peripheral Interface (DSPI) MPC5566 Microcontroller Reference Manual, Rev. 2 20-72 Freescale Semiconductor...
Page 998: Introduction
BAUD ÷16 Data format control bus clock generator Transmit control TDRE generation Transmit shift register TC IRQ Finite state eSCI data register machine TX data out Figure 21-1. eSCI Block Diagram MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 21-1...
Page 999: Overview
• 1/16 bit-time noise detection • Two-channel DMA interface 21.1.4 Modes of Operation The eSCI functions the same in normal, special, and emulation modes. It has a low-power module disable mode. MPC5566 Microcontroller Reference Manual, Rev. 2 21-2 Freescale Semiconductor...
Page 1000: External Signal Description
The total address for each register is the sum of the base address for the eSCI module (ESCIx_base) and the address offset for each register. There are two eSCI modules on this device: • eSCI A base address is 0xFFFB_0000 • eSCI B base address is 0xFFFB_4000 MPC5566 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 21-3...

NXP Semiconductors MPC5566 Reference Manual

Table of Contents

Chapter 1 Introduction

Chapter 3 E200Z6 Core Complex

Chapter 1

Chapter 14

Chapter 15

Figure 2-1. Mpc5566 Signals

Chapter 2

Chapter 3

Chapter 4

Chapter 5 Ripheral Access Control Registers (Pbridge_X_Opacr)

Chapter 7 Slave General-Purpose Control Registers (Xbar_Sgpcrn)

8.2.1 Register Descriptions

Chapter 9

Chapter 10

Chapter 12

Chapter 13 MCR Simultaneous Register Writes

Chapter 16

Chapter 22

Chapter 17 Emios Operating Modes

Chapter 18

Chapter 20

Chapter 23 V por Circuit

Chapter 24

Chapter 25

Appendix A

Appendix B

Appendix C

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