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3.3.2.6 Signal Routing
The Signals routed to the Breakout Board section and IO Link section are described in
HSE Connector
MUX
PRG0_PRU0GPO0
U2
PRG0_PRU0GPO1
PRG0_PRU0GPO2
PRG0_PRU0GPO3
PRG0_PRU0GPO4
PRG0_PRU0GPO5
PRG0_PRU0GPO6
PRG0_PRU0GPO7
PRG0_PRU0GPO8
U4
PRG0_PRU0GPO11
PRG0_PRU0GPO12
PRG0_PRU0GPO13
PRG0_PRU0GPO14
PRG0_PRU0GPO15
PRG0_PRU0GPO16
PRG0_PRU0GPO17
PRG0_PRU1GPO6
U9
PRG0_PRU1GPO8
PRG0_PRU1GPO11
PRG0_PRU1GPO12
PRG0_PRU1GPO13
PRG0_PRU1GPO14
PRG0_PRU1GPO15
PRG0_PRU1GPO16
PRG0_PRU1GPO2
U7
PRG0_PRU0GPO18
PRG0_PRU0GPO19
PRG0_PRU1GPO4
PRG0_PRU1GPO0
PRG0_PRU1GPO1
PRG0_PRU1GPO3
PRG0_PRU1GPO5
GPMC0_ADC0
U11
GPMC0_ADC1
GPMC0_ADC2
GPMC0_ADC3
GPMC0_ADC4
GPMC0_ADC5
GPMC0_ADC6
GPMC0_ADC7
SPRUJ06 – OCTOBER 2021
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Table 3-3. HSE Connector Signal Routing
IO LINK Section
RX_1
RX_2
RX_3
RX_4
RX_5
RX_6
RX_7
RX_8
TX_1
TX_2
TX_3
TX_4
TX_5
TX_6
TX_7
TX_8
EN_PHY_1
EN_PHY_2
EN_PHY_3
EN_PHY_4
EN_PHY_5
EN_PHY_6
EN_PHY_7
EN_PHY_8
EN_L+5
EN_L+1
EN_L+2
EN_L+7
EN_L+3
EN_L+4
EN_L+6
EN_L+8
FAULT_1
FAULT_2
FAULT_3
FAULT_4
FAULT_5
FAULT_6
FAULT_7
FAULT_8
Copyright © 2021 Texas Instruments Incorporated
Table
Breakout Board Section
PRG0_PRU0GPO0_HDR
PRG0_PRU0GPO1_HDR
PRG0_PRU0GPO2_HDR
PRG0_PRU0GPO3_HDR
PRG0_PRU0GPO4_HDR
PRG0_PRU0GPO5_HDR
PRG0_PRU0GPO6_HDR
PRG0_PRU0GPO7_HDR
PRG0_PRU0GPO8_HDR
PRG0_PRU0GPO11_HDR
PRG0_PRU0GPO12_HDR
PRG0_PRU0GPO13_HDR
PRG0_PRU0GPO14_HDR
PRG0_PRU0GPO15_HDR
PRG0_PRU0GPO16_HDR
PRG0_PRU0GPO17_HDR
PRG0_PRU1GPO6_HDR
PRG0_PRU1GPO8_HDR
PRG0_PRU1GPO11_HDR
PRG0_PRU1GPO12_HDR
PRG0_PRU1GPO13_HDR
PRG0_PRU1GPO14_HDR
PRG0_PRU1GPO15_HDR
PRG0_PRU1GPO16_HDR
PRG0_PRU1GPO2_HDR
PRG0_PRU0GPO18_HDR
PRG0_PRU0GPO19_HDR
PRG0_PRU1GPO4_HDR
PRG0_PRU1GPO0_HDR
PRG0_PRU1GPO1_HDR
PRG0_PRU1GPO3_HDR
PRG0_PRU1GPO5_HDR
GPMC0_ADC0_HDR
GPMC0_ADC1_HDR
GPMC0_ADC2_HDR
GPMC0_ADC3_HDR
GPMC0_ADC4_HDR
GPMC0_ADC5_HDR
GPMC0_ADC6_HDR
GPMC0_ADC7_HDR
TMDS64DC01EVM and TMDS243DC01EVM User's Guide
System Description
3-3.
Test Header
J2
J3
J4
J5
J4
J6
9
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