Aaeon GENE-EHL7 User Manual
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Aaeon GENE-EHL7 User Manual

3.5” subcompact board
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GENE-EHL7
3.5" Subcompact Board
User's Manual 1
Ed
st
Last Updated: September 26, 2023

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Summary of Contents for Aaeon GENE-EHL7

  • Page 1 GENE-EHL7 3.5” Subcompact Board User’s Manual 1 Last Updated: September 26, 2023...
  • Page 2 AAEON assumes no liabilities resulting from errors or omissions in this document, or from the use of the information contained herein. AAEON reserves the right to make changes in the product design without notice to its users.
  • Page 3 Acknowledgement All other products’ name or trademarks are properties of their respective owners. Microsoft Windows® is a registered trademark of Microsoft Corp. ⚫ Intel Atom® and Celeron® are registered trademarks of Intel Corporation ⚫ ITE is a trademark of Integrated Technology Express, Inc. ⚫...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity GENE-EHL7 If any of these items are missing or damaged, please contact your distributor or sales representative immediately. Preface...
  • Page 5 (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the product page at AAEON.com for the latest version of this document. Preface...
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.
  • Page 7 If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON Main Board/ Daughter Board/ Backplane 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 ○ ○ ○ ○ 及其电子组件 外部信号 ○ ○ ○ ○ 连接器及线材 O：表示该有毒有害物质在该部件所有均质材料中的含量均在 SJ/T 11363-2006 标准规定的限量要求以下。...
  • Page 10 China RoHS Requirement (EN) Poisonous or Hazardous Substances or Elements in Products AAEON Main Board/ Daughter Board/ Backplane Poisonous or Hazardous Substances or Elements Hexavalent Polybrominated Polybrominated Component Lead Mercury Cadmium Chromium Biphenyls Diphenyl Ethers (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) PCB &...

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications..................1 Specifications ......................2 Block Diagram ......................5 Chapter 2 – Hardware Information ..................6 Dimensions ....................... 7 Jumpers and Connectors ..................8 List of Jumpers ......................9 2.3.1 Clear CMOS Jumper (JP1) ................9 2.3.2 LVDS/eDP BKLT Power Selection (JP2) .............
  • Page 12 2.4.15 Dual USB 3.0 Type-A Connector (CN15) ..........34 2.4.16 Internal USB 2.0 Connectors (CN16/CN17/CN18/CN19) ...... 35 2.4.17 COM Port (RS-232/422/485) (CN20)............36 2.4.18 COM Port (RS-232) (CN21) ................ 39 2.4.19 SPI (For BIOS) (CN22) ................. 40 2.4.20 I2C/SMBus (CN23) ..................40 2.4.21 Debug Port (eSPI) (CN24) ................41 2.4.22...
  • Page 13 3.4.7 Serial Port Console Redirection ..............62 3.4.8 AAEON BIOS Robot ..................63 3.4.9 Device Detecting Configuration ............... 65 3.4.9.1 Device #* Detecting Configuration ..........67 3.4.10 Power Management ..................77 3.4.11 Digital IO Port Configuration ..............78 Setup Submenu: Chipset ..................79 3.5.1...

  • Page 14: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 15: Specifications

    Specifications System Form Factor 3.5" SubCompact Board Intel Atom® x6000E series, Pentium®, and Celeron® N and J Series Processors: Intel Atom® x6413E (4C/4T, 1.50 GHz, 9W) Intel® Celeron® Processor J6412 (4C/4T, 2.00 GHz, 10W) Intel® Celeron® Processor N6210 (2C/2T, 1.20 GHz, 6.5W) Chipset Integrated with Intel®...
  • Page 16 Power Power Requirement +12V Power Supply Type AT/ATX Connector 2-pin Phoenix Connector Power Consumption Intel Atom® x6413E, DDR4 32GB, 2.17A @+12V (Typical) Intel Atom® x6413E, DDR4 32GB, 2.72A @+12V (Max) Display Controller Intel® UHD Graphics for 10th Gen Intel® Processors LVDS/eDP LVDS x 1, Dual Channel 18/24-bit, up to 1920 x 1080 Display Interface...
  • Page 17 Internal I/O USB 2.0 x 4 Serial Port COM 1 (RS-232/422/485, supports 5V/12V/RI) COM 2 (RS-232) Video LVDS/eDP x 1 (Default: LVDS) Inverter x 1 (12V/2A) SATA SATA 6Gb/s x 1 +5V SATA Power Connector x 1 Audio Audio Header x 1 DIO/GPIO GPIO 8-bits SMBus/I2C...

  • Page 18: Block Diagram

    Block Diagram Chapter 1 – Product Specifications...

  • Page 19: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 20: Dimensions

    Dimensions Chapter 2 – Hardware Information...

  • Page 21: Jumpers And Connectors

    Jumpers and Connectors Chapter 2 – Hardware Information...

  • Page 22: List Of Jumpers

    List of Jumpers Please refer to the table below for all of the board’s jumpers that you can configure for your application Label Function Clear CMOS Jumper LVDS/eDP BKLT Power Selection LVDS/eDP Power Selection Auto Power Button Enable/Disable COM 1 Pin 8 Function Selection 2.3.1 Clear CMOS Jumper (JP1) Clear CMOS Jumper...

  • Page 23: Lvds/Edp Bklt Power Selection (Jp2)

    2.3.2 LVDS/eDP BKLT Power Selection (JP2) LVDS/eDP BKLT Power Selection 5V (Default) 2.3.3 LVDS/eDP Power Selection (JP3) LVDS/eDP Power Selection 3.3V (Default) Chapter 2 – Hardware Information...

  • Page 24: Auto Power Button Enable/Disable (Jp4)

    2.3.4 Auto Power Button Enable/Disable (JP4) Auto Power Button Enable/Disable Disable Enable (Default) 2.3.5 COM 1 Pin 8 Function Selection (JP5) COM 1 Pin 8 Function Selection +12V Ring (Default) Chapter 2 – Hardware Information...

  • Page 25: List Of Connectors

    List of Connectors Please refer to the table below for all of the board’s connectors that you can configure for your application Label Function RTC Battery Connector Audio Connector M.2 2280 M-Key M.2 2230 E-Key Mini Card LVDS/eDP Backlight LVDS/eDP Connector HDMI Display Port CN10...
  • Page 26 Label Function CN27 12V Input (4P Colay) CN28 Front Panel CN29 5VB Standby Input CN30 12V Input (New Colay) Chapter 2 – Hardware Information...

  • Page 27: Rtc Battery Connector (Cn1)

    2.4.1 RTC Battery Connector (CN1) Pin Name Signal Type Signal Level +3.3V +3.3V 2.4.2 Audio Connector (CN2) Pin Name Signal Type Signal Level LOUT_R Signal MIC_R Signal LOUT_L Signal MIC_L Signal JD_LOUT Signal JD_MIC Signal AUD_GND AUD_GND Chapter 2 – Hardware Information...

  • Page 28: 2280 M-Key (Cn3)

    Pin Name Signal Type Signal Level JD_LIN Signal LIN_R Signal +V5A_AUD LIN_L Signal AUD_GND AUD_GND 2.4.3 M.2 2280 M-Key (CN3) Pin Name Signal Type Signal Level +V3P3A +3.3V +V3P3A +3.3V PCIE_3_RXN DIFF CARD_PWR_OFF PCIE_3_RXP DIFF Chapter 2 – Hardware Information...
  • Page 29 Pin Name Signal Type Signal Level SSD_LED# PCIE_3_TXN DIFF +V3P3A +3.3V PCIE_3_TXP DIFF +V3P3A +3.3V +V3P3A +3.3V PCIE_2_RXN DIFF +V3P3A +3.3V PCIE_2_RXP DIFF PCIE_2_TXN DIFF PCIE_2_TXP DIFF PCIE_1_RXN DIFF PCIE_1_TXN DIFF Chapter 2 – Hardware Information...
  • Page 30 Pin Name Signal Type Signal Level PCIE_1_TXP DIFF DEVSLP SMCLK PCIE_0_RXN DIFF SMDAT PCIE_0_RXP DIFF PCIE_0_TXN DIFF PCIE_0_TXP DIFF PERST# CLKREQ# PEWARK# PCIE_0_CLK_DN DIFF PCIE_0_CLK_DP DIFF SSCLK PEDET Chapter 2 – Hardware Information...

  • Page 31: 2230 E-Key (Cn4)

    Pin Name Signal Type Signal Level +V3P3A +3.3V +V3P3A +3.3V +V3P3A +3.3V 2.4.4 M.2 2230 E-Key (CN4) Pin Name Signal Type Signal Level +V3P3A +3.3V USB_D+ DIFF +V3P3A +3.3V USB_D- DIFF LED1 Chapter 2 – Hardware Information...
  • Page 32 Pin Name Signal Type Signal Level PCIE_5_TXP DIFF PCIE_5_TXN DIFF PCIE_4_RXP DIFF PCIE_4_RXN DIFF Chapter 2 – Hardware Information...
  • Page 33 Pin Name Signal Type Signal Level PCIE_1_CLK_DP DIFF PCIE_1_CLK_DN DIFF SUSCLK PERST0# PCIE_CLKREQ# W_DISABLE2# PCIE_WAKE# W_DISABLE1# I2C_DATA I2C_CLK Chapter 2 – Hardware Information...

  • Page 34: Mini Card (Cn5)

    Pin Name Signal Type Signal Level +V3P3A_2242 +3.3V +V3P3A_2242 +3.3V +V3P3A_2242 +3.3V 2.4.5 Mini Card (CN5) Pin Name Signal Type Signal Level PCIE_WAKE# +3.3VSB +3.3V +1.5V +1.5V PCIE_CLK_REQ# UIM_PWR Chapter 2 – Hardware Information...
  • Page 35 Pin Name Signal Type Signal Level UIM_DATA PCIE_REF_CLK- DIFF UIM_CLK PCIE_REF_CLK+ DIFF UIM_RST UIM_VPP W_DISABLE# +3.3V BUF_PLT_RST# +3.3V PCIE_RX- DIFF +3.3VSB +3.3V PCIE_RX+ DIFF +1.5V +1.5V SMB_CLK +3.3V PCIE_TX- DIFF SMB_DATA +3.3V PCIE_TX+ DIFF Chapter 2 – Hardware Information...
  • Page 36 Pin Name Signal Type Signal Level USB_D- DIFF USB_D+ DIFF +3.3VSB +3.3V +3.3VSB +3.3V +1.5V +1.5V +3.3VSB +3.3V Chapter 2 – Hardware Information...

  • Page 37: Lvds/Edp Backlight (Cn6)

    2.4.6 LVDS/eDP Backlight (CN6) Pin Name Signal Type Signal Level BKL_PWR +5V / +12V BKL_PWR +5V / +12V BKL_CONTROL BKL_ENABLE Note: LVDS BKL_PWR can be set to +5V or +12V by JP2. 2.4.7 LVDS/eDP Connector (CN7) LVDS Function Pin Name Signal Type Signal Level BKL_ENABLE...
  • Page 38 LVDS Function Pin Name Signal Type Signal Level LVDSA_CLK# DIFF +3.3V/+5V LVDSA_CLK DIFF +3.3V/+5V LVDSA_DATA0# DIFF LVDSA_DATA2# DIFF LVDSA_DATA0 DIFF LVDSA_DATA2 DIFF LVDSA_DATA1# DIFF LVDSA_DATA3# DIFF LVDSA_DATA1 DIFF LVDSA_DATA3 DIFF LVDSB_D0# DIFF LVDS_DDC_DATA LVDSB_D0 DIFF LVDS_DDC_CLK Chapter 2 – Hardware Information...
  • Page 39 LVDS Function Pin Name Signal Type Signal Level LVDSB_DATA1# DIFF LVDSB_DATA2# DIFF LVDSB_DATA1 DIFF LVDSB_DATA2 DIFF LVDSB_CLK# DIFF LVDSB_DATA3# DIFF LVDSB_CLK DIFF LVDSB_DATA3 DIFF EDP _LVDS_ HPD eDP Function Pin Name Signal Type Signal Level BKL_ENABLE BKL_CONTROL DDI0_LANE3_DN DIFF +3.3V/+5V DDI0_LANE3_DP DIFF +3.3V/+5V...
  • Page 40 eDP Function Pin Name Signal Type Signal Level DDI0_LANE2_DN DIFF DDI0_LANE0_DN DIFF DDI0_LANE2_DP DIFF DDI0_LANE0_DP DIFF DDI0_LANE1_DN DIFF DDI0_LANE1_DP DIFF Chapter 2 – Hardware Information...

  • Page 41: Hdmi (Cn8)

    eDP Function Pin Name Signal Type Signal Level EDP _LVDS_ HPD Note: LVDS/eDP LCD_PWR can be set to +3.3V or +5V by JP3. 2.4.8 HDMI (CN8) Pin Name Signal Type Signal Level HDMI_TX2+ DIFF HDMI_TX2- DIFF HDMI_TX1+ DIFF HDMI_TX1- DIFF HDMI_TX0+ DIFF HDMI_TX0-...

  • Page 42: Display Port (Cn9)

    Pin Name Signal Type Signal Level HDMI_CLK+ DIFF HDMI_CLK- DIFF DDC_CLK Signal DDC_DATA Signal HDMI_HPD 2.4.9 Display Port (CN9) Pin Name Signal Type Signal Level DP_D0_P DIFF DP_D0_N DIFF DP_D1_P DIFF DP_D1_N DIFF DP_D2_P DIFF Chapter 2 – Hardware Information...

  • Page 43: Cn10)

    Pin Name Signal Type Signal Level DP_D2_N DIFF DP_D3_P DIFF DP_D3_N DIFF DP_AUX_P Signal DP_AUX_N Signal Signal RTN_PWR 3.3V 2.4.10 RJ-45 (CN10) Pin Name Signal Type Signal Level LAN1_MDI0+ DIFF LAN1_MDI0- DIFF LAN1_MDI1+ DIFF LAN1_MDI1- DIFF LAN1_CT Chapter 2 – Hardware Information...

  • Page 44: Cn11)

    Pin Name Signal Type Signal Level LAN1_CT LAN1_MDI2+ DIFF LAN1_MDI2- DIFF LAN1_MDI3+ DIFF LAN1_MDI3- DIFF LAN1_LED_LNK#_ACT Signal +V3P3A +3.3V LAN1_LED_100# Signal LAN1_LED_1000# Signal 2.4.11 RJ-45 (CN11) Pin Name Signal Type Signal Level LAN2_MDI0+ DIFF LAN2_MDI0- DIFF LAN2_MDI1+ DIFF LAN2_MDI1- DIFF LAN2_CT LAN2_CT LAN2_MDI2+...

  • Page 45: Sata (Cn12)

    Pin Name Signal Type Signal Level LAN2_MDI3- DIFF LAN2_LED_LNK#_ACT Signal +V3P3A +3.3V LAN2_LED_100# Signal LAN2_LED_1000# Signal 2.4.12 SATA (CN12) Pin Name Signal Type Signal Level SATA_1_TXP DIFF SATA_1_TXN DIFF SATA_1_RXN DIFF SATA_1_RXP DIFF Chapter 2 – Hardware Information...

  • Page 46: Sata Power (Cn13)

    2.4.13 SATA Power (CN13) Pin Name Signal Type Signal Level +V5S Note: SATA power current max: 1.5A. 2.4.14 GPIO Connector (CN14) Pin Name Signal Type Signal Level GPIO_0 Signal GPIO_1 Signal GPIO_2 Signal GPIO_3 Signal GPIO_4 Signal Chapter 2 – Hardware Information...

  • Page 47: Dual Usb 3.0 Type-A Connector (Cn15)

    Pin Name Signal Type Signal Level GPIO_5 Signal GPIO_6 Signal GPIO_7 Signal +V5S Note: GPIO power current max: 0.5A. 2.4.15 Dual USB 3.0 Type-A Connector (CN15) Pin Name Signal Type Signal Level +V5A_USB12 USB2_0_DN DIFF USB2_0_DP DIFF USB3_0_RXN DIFF USB3_0_RXP DIFF USB3_0_TXN DIFF...

  • Page 48: Internal Usb 2.0 Connectors (Cn16/Cn17/Cn18/Cn19)

    Pin Name Signal Type Signal Level +V5A_USB12 USB2_1_DN DIFF USB2_1_DP DIFF USB3_1_RXN DIFF USB3_1_RXP DIFF USB3_1_TXN DIFF USB3_1_TXP DIFF Note: USB 3.0 power current max: 0.9A. 2.4.16 Internal USB 2.0 Connectors (CN16/CN17/CN18/CN19) Pin Name Signal Type Signal Level +5VSB DIFF DIFF Note: Each USB 2.0 power current max: 0.5A.

  • Page 49: Com Port (Rs-232/422/485) (Cn20)

    2.4.17 COM Port (RS-232/422/485) (CN20) RI/+5V/+12V RS-232 Pin Name Signal Type Signal Level ±9V ±9V ±9V RI/+5V/+12V IN/ PWR +5V/+12V Chapter 2 – Hardware Information...
  • Page 50 RS-485 Pin Name Signal Type Signal Level RS485_D- ±5V RS485_D+ ±5V NC/+5V/+12V +5V/+12V Chapter 2 – Hardware Information...
  • Page 51 RS422_TX- RS422_TX+ RS422_RX+ RS422_RX- NC/+5V/+12V RS-422 Pin Name Signal Type Signal Level RS422_TX- ±5V RS422_TX+ ±5V RS422_RX+ RS422_RX- NC/+5V/+12V +5V/+12V Note: RS-232/422/485 can be set by BIOS setting. Default is RS-232. Note: Pin 8 function can be set by JP5. Chapter 2 –...

  • Page 52: Com Port (Rs-232) (Cn21)

    2.4.18 COM Port (RS-232) (CN21) RS-232 Pin Name Signal Type Signal Level ±9V ±9V ±9V Chapter 2 – Hardware Information...

  • Page 53: Spi (For Bios) (Cn22)

    2.4.19 SPI (For BIOS) (CN22) Pin Name Signal Type Signal Level SPI_SO Signal SPI_CLK Signal +V3P3A_SPI +3.3V SPI_SI Signal SPI_CS Signal 2.4.20 I2C/SMBus (CN23) Pin Name Signal Type Signal Level 3.3V SMB_CLK / I2C_CLK DIFF SMB_SDA/ I2C_DATA DIFF SMB_ALERT#/ INT_SERIRQ Chapter 2 –...

  • Page 54: Debug Port (Espi) (Cn24)

    2.4.21 Debug Port (eSPI) (CN24) Pin Name Signal Type Signal Level ESPI_IO0 Signal +1.8V ESPI_IO1 Signal +1.8V ESPI_IO2 Signal +1.8V ESPI_IO3 Signal +1.8V +V3.3S +3.3V ESPI_CS Signal ESPI_RESET# Signal +1.8V ESPI_CLK Signal 1.8V +V3P3A POWER +3.3V 2.4.22 Fan Connector (CN25) Pin Name Signal Type Signal Level...

  • Page 55: Power Input (Cn26/Cn30)

    Note: Smart FAN power current max: 1.0A. 2.4.23 Power Input (CN26/CN30) Pin Name Signal Type Signal Level +V_IN +12V Note: Colay CN30. 2.4.24 ATX-2X2P Input [Reserved] (CN27) Pin Name Signal Type Signal Level +V_IN +12V +V_IN +12V Note: CN27 only for +12V. Chapter 2 –...

  • Page 56: Front Panel (Cn28)

    2.4.25 Front Panel (CN28) Pin Name Signal Type Signal Level EXT_PWRBTN# Signal FP_IDELED# Signal +V3P3S +3.3V FP_BUZZER Signal +V5S +V3P3S +3.3V HWRST# Signal Chapter 2 – Hardware Information...

  • Page 57: 5Vb Standby Input (Cn29)

    2.4.26 5VB Standby Input (CN29) Pin Name Signal Type Signal Level PS_ON# Signal +V5A_SB_IN Chapter 2 – Hardware Information...

  • Page 58: Thermal Solution

    Thermal Solution Optional accessory: GENE-EHL7-HSK01 Chapter 2 – Hardware Information...

  • Page 59: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 60: System Test And Initialization

    System Test and Initialization The GENE-EHL7 uses certain routines to perform testing and initialization during the boot up sequence. If an error, fatal or non-fatal, is encountered, the module will output a few short beeps or display an error message. The module can usually continue the boot up sequence with non-fatal errors.

  • Page 61: Ami Bios Setup

    AMI BIOS Setup The AMI BIOS ROM has a pre-installed Setup program that allows users to modify basic system configurations, which is stored in the battery-backed CMOS RAM and BIOS NVRAM so that the information is retained when the power is turned off. To enter BIOS Setup, press <Del>...

  • Page 62: Setup Submenu: Main

    Setup Submenu: Main Chapter 3 – AMI BIOS Setup...

  • Page 63: Setup Submenu: Advanced

    Setup Submenu: Advanced Chapter 3 – AMI BIOS Setup...

  • Page 64: Cpu Configuration

    3.4.1 CPU Configuration Options Summary Active Processor Cores Optimal Default, Failsafe Default Number of cores to enable in each processor package. Intel (VMX) Virtualization Disabled Technology Enabled Optimal Default, Failsafe Default When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.

  • Page 65: Pch-Fw Configuration

    3.4.2 PCH-FW Configuration Chapter 3 – AMI BIOS Setup...

  • Page 66: Firmware Update Configuration

    3.4.2.1 Firmware Update Configuration Options Summary Me FW Image Re-Flash Enabled Disabled Optimal Default, Failsafe Default Enable/Disable Me FW Image Re-Flash function. FW Update Disabled Enabled Optimal Default, Failsafe Default Enable/Disable ME FW Update function. Chapter 3 – AMI BIOS Setup...

  • Page 67: Trusted Computing

    3.4.3 Trusted Computing Options Summary Security Device Support Enable Optimal Default, Failsafe Default Disable Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. SHA-1 PCR Bank Disabled Optimal Default, Failsafe Default Enabled...
  • Page 68 Options Summary Enable or Disable SM3_256 PCR Bank. Pending operation None Optimal Default, Failsafe Default TPM Clear Schedule an Operation for the Security Device. NOTE: Your Computer will reboot during restart in order to change State of Security Device. Platform Hierarchy Enabled Optimal Default, Failsafe Default Disabled...

  • Page 69: Sata Configuration

    3.4.4 SATA Configuration Options Summary SATA Controller(s) Enabled Optimal Default, Failsafe Default Disabled Enable/Disable SATA Device. Port* Enabled Optimal Default, Failsafe Default Disabled Enable or Disable SATA Port. Chapter 3 – AMI BIOS Setup...

  • Page 70: Hardware Monitor

    3.4.5 Hardware Monitor Options Summary Smart Fan Disable Enable Optimal Default, Failsafe Default Enables or Disables Smart Fan. Chapter 3 – AMI BIOS Setup...

  • Page 71: Smart Fan Mode Configuration

    3.4.5.1 Smart Fan Mode Configuration Options Summary FAN1 Output Mode Output PWM mode (open drain) Linear Fan Application Output PWM mode Optimal Default, Failsafe Default (push pull) Fan 1 Smart Fan Control Manual Duty Mode Auto Duty-Cycle Mode Optimal Default, Failsafe Default Smart Fan Mode Select.

  • Page 72: Sio Configuration

    Options Summary Auto fan speed control. Fan speed will follow different temperature by different duty cycle 1-100. 3.4.6 SIO Configuration Chapter 3 – AMI BIOS Setup...

  • Page 73: Serial Port 1 Configuration

    3.4.6.1 Serial Port 1 Configuration Options Summary Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=3F8h; IRQ=4 IO=2F8h; IRQ=3 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 74: Serial Port 2 Configuration

    3.4.6.2 Serial Port 2 Configuration Options Summary Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=2F8h; IRQ=3 IO=3F8h; IRQ=4 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 75: Serial Port Console Redirection

    3.4.7 Serial Port Console Redirection Options Summary Console Redirection Disabled Optimal Default, Failsafe Default Enabled Console Redirection Enable or Disable. Console Redirection EMS Disabled Optimal Default, Failsafe Default Enabled Console Redirection Enable or Disable. Chapter 3 – AMI BIOS Setup...

  • Page 76: Aaeon Bios Robot

    3.4.8 AAEON BIOS Robot Options Summary Sends watch dog before Disabled Optimal Default, Failsafe Default BIOS POST Enabled Enabled - Robot set Watch Dog Timer (WDT) right after power on, before BIOS start POST process. And then Robot will clear WDT on completion of POST. WDT will reset system automatically if it is not cleared before its timer counts down to zero.
  • Page 77 Options Summary OS Timer (minute) Optimal Default, Failsafe Default Timer count set to Watch Dog Timer for OS loading. Delayed POST (PEI phase) Disabled Optimal Default, Failsafe Default Enabled Enabled - Robot holds BIOS from starting POST, right after power on. This allows BIOS POST to start with stable power or start after system is physically warmed-up.

  • Page 78: Device Detecting Configuration

    3.4.9 Device Detecting Configuration Options Summary Action Reset System Optimal Default, Failsafe Default Hold System Select action that robot should do. Soft or hard reset Soft Optimal Default, Failsafe Default Hard Select reset type robot should send on each boot. Retry-Count Optimal Default, Failsafe Default Fill retry counter here.
  • Page 79 Options Summary Action Reset System Optimal Default, Failsafe Default Hold System Select action that robot should do. Holding time out (second) Optimal Default, Failsafe Default Fill hold time out here. Robot will hold system no longer then time-out value, and then let system continue its POST.

  • Page 80: Device #* Detecting Configuration

    3.4.9.1 Device #* Detecting Configuration Options Summary Interface Disabled Optimal Default, Failsafe Default SMBUS Legacy I/O Super I/O MMIO Select interface robot should use to communicate with device. Chapter 3 – AMI BIOS Setup...
  • Page 81 Options Summary: "PCI" Optimal Default, Failsafe Default Fill BUS number to a PCI device, in hexadecimal. Range: 0 – FF. Device Optimal Default, Failsafe Default Fill DEVICE number to a PCI device, in hexadecimal. Range: 0 – FF. Function Optimal Default, Failsafe Default Fill FUNCTION number to a PCI device, in hexadecimal.
  • Page 82 Options Summary: "PCI" Register data is bitwise equal to Optimal Default, Failsafe Default bytewise equal to bytewise lesser than bytewise larger than Select how robot should compare data read from register, to a value configured below. Register offset Optimal Default, Failsafe Default Fill register offset (or index) for robot to read, in hexadecimal.
  • Page 83 Options Summary: "DIO" Device Is not Optimal Default, Failsafe Default Select that robot should or should not do action if condition met. DIO pin DIO1 Optimal Default, Failsafe Default DIO* Fill DIO pin number. 0 - DIO01 - DIO1\n... and so on. For COM express product: \0-3 - GPI0-3\n4-7 - GPO0-3.
  • Page 84 Options Summary: "SMBUS" SMBUS Slave Address Optimal Default, Failsafe Default Fill slave address to a SMBUS device, in hexadecimal. Range: 0 – FF. Device Is not Optimal Default, Failsafe Default Select that robot should or should not do action if condition met. In condition Present Optimal Default, Failsafe Default...
  • Page 85 Options Summary: "SMBUS" Bit offset Optimal Default, Failsafe Default Fill bit offset for register, for robot to compare with bit value. Bit value Optimal Default, Failsafe Default High Fill bit value for robot to compare register-bit with specified offset. Byte value Optimal Default, Failsafe Default Fill a byte value for robot to compare register data with, in hexadecimal.
  • Page 86 Options Summary: "Legacy I/O" Select the condition that robot should check for device. Present - device is detected. According to register - Robot read register according to configuration. Note: Device will be considered 'Present' by Robot, when data read from device is not 0xFF. Register data is bitwise equal to Optimal Default, Failsafe Default...
  • Page 87 Options Summary: "Super I/O" Super I/O LDN Optimal Default, Failsafe Default Fill LDN number to a Super I/O device. Range: 0~FF. Device Is not Optimal Default, Failsafe Default Select that robot should or should not do action if condition met. In condition Present Optimal Default, Failsafe Default...
  • Page 88 Options Summary: "Super I/O" Bit offset Optimal Default, Failsafe Default Fill bit offset for register, for robot to compare with bit value. Bit value Optimal Default, Failsafe Default High Fill bit value for robot to compare register-bit with specified offset. Byte value Optimal Default, Failsafe Default Fill a byte value for robot to compare register data with, in hexadecimal.
  • Page 89 Options Summary: "MMIO" Select the condition that robot should check for device. Present - device is detected. According to register - Robot read register according to configuration. Note: Device will be considered 'Present' by Robot, when data read from device is not 0xFF. Register data is bitwise equal to Optimal Default, Failsafe Default...

  • Page 90: Power Management

    3.4.10 Power Management Options Summary: Power Mode ATX Type Optimal Default, Failsafe Default AT Type Select power supply mode. Restore AC Power Loss Last State Optimal Default, Failsafe Default Always On Always Off Select power state when power is re-applied after a power failure. RTC wake system from S5 Disable Optimal Default, Failsafe Default...

  • Page 91: Digital Io Port Configuration

    3.4.11 Digital IO Port Configuration Options Summary: GPIO Port* Output Input Set GPIO as Input or Output. Output Level High Set output level when GPIO pin is output. Chapter 3 – AMI BIOS Setup...

  • Page 92: Setup Submenu: Chipset

    Setup Submenu: Chipset Chapter 3 – AMI BIOS Setup...

  • Page 93: System Agent (Sa) Configuration

    3.5.1 System Agent (SA) Configuration Options Summary: VT-d Disabled Enabled Optimal Default, Failsafe Default VT-d capability. Chapter 3 – AMI BIOS Setup...

  • Page 94: Memory Configuration

    3.5.1.1 Memory Configuration Chapter 3 – AMI BIOS Setup...

  • Page 95: Lvds Panel Configuration

    3.5.1.2 LVDS Panel Configuration Options Summary: LVDS Disabled Enabled Optimal Default, Failsafe Default Enabled/Disabled this panel. LCD Panel Type 640x480@60Hz 800x480@60Hz 800x600@60Hz 1024x600@60Hz 1024x768@60Hz Optimal Default, Failsafe Default 1280x768@60Hz 1280x800@60Hz 1280x1024@60Hz 1366x768@60Hz 1440x900@60Hz 1600x1200@60Hz Chapter 3 – AMI BIOS Setup...
  • Page 96 Options Summary: LCD Panel Type cont. 1920x1080@60Hz 1920x1200@60Hz Select LCD panel used by internal graphics device by selecting the appropriate setup item. Color Depth 18-Bit Optimal Default, Failsafe Default 24-Bit 36-Bit 48-Bit Select panel type. Backlight Mode BIOS & Application Window Slider Optimal Default, Failsafe Default Select backlight control signal type.

  • Page 97: Pci Express Configuration

    3.5.2 PCI Express Configuration Chapter 3 – AMI BIOS Setup...

  • Page 98: Pcie Slot M.2 Key-E 2230 (Cn4)

    3.5.2.1 Pcie Slot M.2 KEY-E 2230 (CN4) Options Summary: Pcie Slot M.2 KEY-E 2230 Disabled (CN4) Enabled Optimal Default, Failsafe Default Control the PCI Express Root Port. Pcie Slot M.2 KEY-E 2230 Auto Optimal Default, Failsafe Default (CN4) Gen1 Gen2 Gen3 Configure PCIe Speed.

  • Page 99: Pcie Slot M.2 Key-E 2280 (Cn3)

    3.5.2.2 Pcie Slot M.2 KEY-E 2280 (CN3) Options Summary: Pcie Slot M.2 KEY-E 2280 Disabled (CN3) Enabled Optimal Default, Failsafe Default Control the PCI Express Root Port. Pcie Slot M.2 KEY-E 2280 Auto Optimal Default, Failsafe Default (CN3) Gen1 Gen2 Gen3 Configure PCIe Speed.

  • Page 100: Setup Submenu: Security

    Setup Submenu: Security Change User/Administrator Password You can set an Administrator Password or User Password. An Administrator Password must be set before you can set a User Password. The password will be required during boot up, or when the user enters the Setup utility. A User Password does not provide access to many of the features in the Setup utility.

  • Page 101: Secure Boot

    3.6.1 Secure Boot Options Summary Secure Boot Disabled Optimal Default, Failsafe Default Enabled Secure Boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled and the System is in User mode. The mode change requires platform reset. Secure Boot Mode Custom Optimal Default, Failsafe Default...

  • Page 102: Key Management

    3.6.1.1 Key Management Options Summary: Factory Key Provision Disabled Optimal Default, Failsafe Default Enabled Secure Boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled and the System is in User mode. The mode change requires platform reset. Restore Factory Keys Force System to User Mode.
  • Page 103 Options Summary: Remove 'UEFI CA' from DB Device Guard ready system must not list 'Microsoft UEFI CA' Certificate in Authorized Signature database (db). Restore DB defaults Restore DB variable to factory defaults. Platform Key(PK) Details Export Update Delete Key Exchange Keys Details Export Update...

  • Page 104: Setup Submenu: Boot

    Setup Submenu: Boot Options Summary: Quiet Boot Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Quiet Boot option. UEFI PXE Support Disabled Optimal Default, Failsafe Default Enabled Enable/Disable UEFI Network Stack. FIXED BOOT ORDER Priorities Sets the system boot order. Chapter 3 –...

  • Page 105: Bbs Priorities

    3.7.1 BBS Priorities Chapter 3 – AMI BIOS Setup...

  • Page 106: Setup Submenu: Save & Exit

    Setup Submenu: Save & Exit Options Summary: Save Changes and Reset Reset the system after saving the changes. Discard Changes and Exit Exit system setup without saving any changes. Restore Defaults Restore/Load Default values for all the setup options. Chapter 3 – AMI BIOS Setup...

  • Page 107: Chapter 4 - Driver Installation

    Chapter 4 Chapter 4 – Driver Installation...

  • Page 108: Driver Download/Installation

    Driver Download/Installation Drivers for the GENE-EHL7 can be downloaded from the product page on the AAEON website by following this link: https://www.aaeon.com/en/ Download the driver(s) you need and follow the steps below to install them. Install Chipset Drivers Open the Intel Chipset folder Run the SetupChipset.exe in the folder...
  • Page 109 Install Audio Driver Open the Audio folder Run the Setup.exe file in the folder Follow the instructions Drivers will be installed automatically Install Serial IO Drivers Open the Serial IO folder Follow the instructions Drivers will be installed automatically Install ME Drivers Open the ME folder Run the SetupME.exe file in the folder Follow the instructions...

  • Page 110: Appendix A - I/O Information

    Appendix A Appendix A - I/O Information...

  • Page 111: I/O Address Map

    I/O Address Map Appendix A – I/O Information...
  • Page 112 Appendix A – I/O Information...

  • Page 113: A.2 Memory Address Map

    A.2 Memory Address Map Appendix A – I/O Information...
  • Page 114 Appendix A – I/O Information...

  • Page 115: A.3 Irq Mapping Chart

    A.3 IRQ Mapping Chart Appendix A – I/O Information...
  • Page 116 Appendix A – I/O Information...
  • Page 117 Appendix A – I/O Information...

  • Page 118: Appendix B - Mating Connectors And Cables

    Appendix B Appendix B – Mating Connectors and Cables...

  • Page 119: Mating Connectors And Cables

    Mating Connectors and Cables Mating Connector Conn Function Available Cable Cable P/N Label Vendor Model No. RTC Battery Molex 51021-0200 Battery Cable 175011301C Audio Audio cable 170X000156 LVDS/eDP Port Inverter/ WL1010H-6P LVDS Inverter Cable 170X000152 Backlight Connector LVDS SHDR WL1010H-2*2 LVDS Cable 170X000280 JCTC...

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