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FemtoClock®2 GUI User Guide
3.2
DPLL
If the device is configured for jitter attenuator mode, the DPLL section will become available. The DPLL section
allows users to manually adjust bandwidth, decimator, gain peaking, and phase slope limit values. Alternatively,
the user can select a predefined SyncE profile that will automatically populate the adjustable settings.
Descriptions of each section and the SyncE profiles are on the right of the page.
R31US0004EU0100 Rev.1.0
Apr 22, 2021
Page 6
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