Quectel SC20 Series Hardware Design page 36

Smart Module Series
below 3.1 V.
Figure 3: Voltage Drop Sample
To decrease voltage drop, a bypass capacitor of about 100 µF with low ESR (ESR = 0.7 Ω) should be
used, and a multi-layer ceramic chip capacitor (MLCC) should also be reserved due to its ultra-low ESR. It
is recommended to use three ceramic capacitors (100 nF, 33 pF, 10 pF) for composing the MLCC array,
and place these capacitors close to VBAT_BB/VBAT_RF pins. The main power supply from the external
application must be a single voltage source and can be expanded to two sub paths with star structure.
The width of VBAT_BB trace should be no less than 1.5 mm, and the width of VBAT_RF trace should be
no less than 2 mm. In principle, the longer the VBAT trace is, the wider it should be.
In addition, in order to get a stable power source, it is suggested to use a TVS diode and place it as close
to the VBAT_BB/VBAT_RF pins as possible to increase voltage surge withstand capability. The following
figure shows the star structure of the power supply.
VBAT
VBAT_RF
VBAT_BB
+
+
C5
C4 C6 C7 C8
C2 C3
C1
D1
100 nF 33 pF 10 pF 100 μ F 100 nF 33 pF 10 pF
100 μF
Module
Figure 4: Star Structure of the Power Supply
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