Quectel SC20 Series Hardware Design page 46

UART2_RX 93
UART2_TX 94
UART1 provides 1.8 V logic level. A level translator should be used if your application is equipped with a
3.3 V UART interface. A level translator TXS0104PWR provided by Texas Instruments is recommended.
The following figure shows the reference design.
LDO5_1V8
UART1_CTS
UART1_RTS
UART1_TX
UART1_RX
Figure 15: Reference Circuit with Level Translator Chip (for UART1)
The following figure is an example of connection between the module and PC. A voltage level translator
and a RS-232 level translator chip are recommended to be added between the module and PC.
SC20_Series_Hardware_Design
UART2 receive;
DI
Debug port by default
UART2 transmit;
DO
Debug port by default
VCCA
C1
100 pF
OE
A1
A2
TXS0104EPWR
A3
A4
Figure 16: RS-232 Level Match Circuit (for UART1)
VCCB
U1
GND
B1
B2
B3
B4
Smart Module Series
If unused, keep these pins
open.
1.8 V power domain.
If it is unused, keep it open.
VDD_3.3V
C2
100 pF
CTS_3.3V
RTS_3.3V
TXD_3.3V
RXD_3.3V
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