Options; Figure 2. Total Reach Dds Circuit Diagram; Figure 3. Option Switch; Table 1. Option Settings - ADTRAN Total Reach DDS-DP 5 Series Installation And Maintenance Manual
Total reach all-rate dds dataport
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SLC
SERIES 5
DLC
2-Wire Loop
T-Carrier
DDS-DP
T/R Pair
Figure 2. Total Reach DDS Circuit Diagram
Features
• 2-wire deployment
• Repeaterless operation
• Bridged tap tolerant
• Span power for remote DDS-R termination unit
• Utilization in SLC Series 5 channel bank
• Loop Quality Monitor and A/B signaling options
• Bidirectional OCU loopback capability
• False latching loopback prevention at 64 kbps
• Response to remote end initiated loopback
2. OPTIONS
The Series 5 DDS-DP is provisioned through the SLC
Series 5 system and circuit board DIP switch SW2.
This arrangement provides feature options not
available through the SLC Series 5 channel bank
intelligent system. Use the SLC Series 5 Craft
Interface Unit (CIU) to provision intelligent channel
bank features supported by the Series 5 Total Reach
DDS-DP. See Figure 3 and Table 1 for option
description and provisioning.
Select OCU DP, CLEI 5SCU48, when
provisioning via the CIU.
Figure 3. Option Switch
Error Correction
When Error Correction is enabled, the DDS-DP
provides an error detection and correction capability
that maintains data integrity across the carrier facility.
2
Customer Premises
4-Wire Customer
Interface
DDS-R
DSU/CSU
NOTE
64K
19.2K
SW56
ABSIG
QM
Section 61433105L1, Issue 6
Table 1. Option Settings
S
o
t f
w
a
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P
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v
s i
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F
u
n
t c
o i
n
R
a
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e S
e l
t c
E
r r
r o
C
r o
e r
i t c
n o
f I
a r
e t
E (
) C
M
V
E
C
v a
l i a
b a
f I
a r
e t
S
C
E
C
t
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e s
a r
Z
e
o r
C
o
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Z (
) C
Y
s e
r o
S
c e
n o
a d
y r
Y
s e
r o
C
a h
n n
l e
S (
) C
H
a
d r
w
a
e r
P
r
v o
s i
o i
4 6
K
S
W
2
1 -
O
N
s
l e
1
9 1
2 .
K
S
W
2
2 -
O
N
s
l e
S
w
t i
h c
d e
6 5
S
W
2
3 -
O
N
e
a n
O
F
F
i d
A
B /
i S
n g
i l a
g n
S
W
2
4 -
O
N
t
e h
t
e h
A
s
g i
a n
s l
a b
k c
l p
O
F
F
t
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t
e h
n i
o c
Q
u
i l a
y t
M
n o
t i
r o
S
W
2
5 -
O
N
e
a n
O
F
F
i d
1
F
r o
9 1
2 .
b k
s p
E
r r
r o
C
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n e
b a
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9
6 .
M
V
E
C
i w
h t
S
For subrate and 19.2 kbps rates, error correction and
data transmission is accomplished over a single DS0
time slot using a Majority Vote Error Correction
(MVEC) algorithm. For error correction at these
rates, MVEC must be selected in the BCU via the
SLC Series 5 CIU.
For rates of 56 and 64 kbps, error correction requires
one additional DS0 time slot for the error correcting
parity byte. The DDS-DP only allows SCEC, the
parity byte error correction scheme, at 56 and 64 kbps.
When error correction is desired for 19.2 kbps service,
provision 9.6 kbps and MVEC via the CIU and select
19.2K on SW2.
n
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5
B
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4 .
4 ,
8 .
9 ,
, 6 .
r o
6 5
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4 .
t
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u o
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9 1
, 2 .
e s
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: t c
r o
N
O
N
E
S (
C
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a
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r
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t
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4 6
k
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N
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(
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N
o
N
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4 6
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