ADLINK Technology COM Express Express-BD7 User Manual page 24

3.3.12. General Purpose I/O (GPIO)
Signal Pin Description
GPO[0] A93 General purpose output pins.
GPO[1] B54 General purpose output pins.
GPO[2] B57 General purpose output pins.
GPO[3] B63 General purpose output pins.
GPI[0] A54 General purpose input pins.
Pulled high internally on the module.
General purpose input pins.
GPI[1] A63
Pulled high internally on the module.
GPI[2] A67 General purpose input pins.
Pulled high internally on the module.
GPI[3] A85 General purpose input pins.
Pulled high internally on the module.
3.3.13. Serial Interface Signals
Signal Pin Description
SER0_TX A98 General purpose serial port transmitter (TTL level
output)
SER0_RX A99 General purpose serial port receiver (TTL level
input)
SER1_TX A101 General purpose serial port transmitter (TTL level
output)
SER1_RX A102 General purpose serial port receiver (TTL level
input)
3.3.14. Power and System Management
Signal Pin
PWRBTN# B12
SYS_RESET# B49
CB_RESET# B50
PWR_OK B24
18
Description
Power button to bring system out of S5 (soft off), active on
falling edge.
Reset button input. Active low request for module to reset
and reboot. May be falling edge sensitive. For situations
when SYS_RESET# is not able to reestablish control of the
system, PWR_OK or a power cycle may be used.
Reset output from module to Carrier Board. Active low.
Issued by module chipset and may result from a low
SYS_RESET# input, a low PWR_OK input, a VCC_12V
power input that falls below the minimum specification, a
watchdog timeout, or may be initiated by the module
software.
Power OK from main power supply. A high value indicates
that the power is good. This signal can be used to hold off
Module startup to allow carrier based FPGAs or other
configurable devices time to be programmed.
I/O PU/PD
O 3.3V PU 10K 3.3V
O 3.3V PU 10K 3.3V
O 3.3V PU 10K 3.3V
O 3.3V PU 10K 3.3V
I 3.3V PU 10K 3.3V
I 3.3V PU 10K 3.3V
I 3.3V PU 10K 3.3V
I 3.3V PU 10K 3.3V
I/O PU/PD
O CMOS PU 10k 5V Power rail tolerance
I CMOS PU 10k 5V Power rail tolerance
O CMOS PU 10k 5V Power rail tolerance
I CMOS PU 10k 5V Power rail tolerance
I/O
I 3.3VSB
I 3.3VSB
O 3.3V
I 3.3VSB
Pinouts and Signal Descriptions
Comment
After hardware
RESET output low
After hardware
RESET output low
After hardware
RESET output low
After hardware
RESET output low
Comment
5V, 12V
5V, 12V
5V, 12V
5V, 12V
PU/PD Comment
PU 10k
3.3VSB
PU 10k
3.3VSB
PU 1k Should
3.3VSB have weak
pull up