ADLINK Technology COM Express Express-BD7 User Manual page 21

Signal Pin
PCIE_TX10+ A77
PCIE_TX10- A78
PCIE_RX10+ B77
PCIE_RX10- B78
PCIE_TX11+ A81
PCIE_TX11- A82
PCIE_RX11+ B81
PCIE_RX11- B82
PCIE_TX12+ A39
PCIE_TX12- A40
PCIE_RX12+ B39
PCIE_RX12- B40
PCIE_TX13+ A36
PCIE_TX13- A37
PCIE_RX13+ B36
PCIE_RX13- B37
PCIE_TX14+ A25
PCIE_TX14- A26
PCIE_RX14+ B25
PCIE_RX14- B26
PCIE_TX15+ A22
PCIE_TX15- A23
PCIE_RX15+ B22
PCIE_RX15- B23
PCIE_CLK_REF+ A88
PCIE_CLK_REF- A89
3.3.5. LPC Bus
Signal Pin
LPC_AD[0:3] B4-B7
LPC_FRAME# B3
LPC_DRQ0# B8
LPC_DRQ1# B9
LPC_SERIRQ A50
LPC_CLK B10
Note: eSPI and LPC buses are muxed. Express-BD7 module only supports LPC interface.
3.3.6. USB
Signal Pin
USB0+ A46
USB0- A45
Pinouts and Signal Descriptions
Description
PCI Express channel 10, Transmit
Output differential pair.
PCI Express channel 10, Receive
Input differential pair.
PCI Express channel 11, Transmit
Output differential pair.
PCI Express channel 11, Receive
Input differential pair.
PCI Express channel 12, Transmit
Output differential pair.
PCI Express channel 12, Receive
Input differential pair.
PCI Express channel 13, Transmit
Output differential pair.
PCI Express channel 13, Receive
Input differential pair.
PCI Express channel 14, Transmit
Output differential pair.
PCI Express channel 14, Receive
Input differential pair.
PCI Express channel 15, Transmit
Output differential pair.
PCI Express channel 15, Receive
Input differential pair.
PCI Express Reference Clock
output for all PCI Express and PCI
Express Graphics Lanes.
Description
LPC multiplexed address, command
and data bus
LPC frame indicates the start of an
LPC cycle
LPC serial DMA request
LPC serial interrupt
LPC clock output –33MHz nominal
Description
USB differential data pairs for Port 0
I/O PU/PD Comment
O PCIE AC coupled on Module
I PCIE AC coupled off Module
O PCIE AC coupled on Module
I PCIE AC coupled off Module
O PCIE AC coupled on Module
I PCIE AC coupled off Module
O PCIE AC coupled on Module
I PCIE AC coupled off Module
O PCIE AC coupled on Module
I PCIE AC coupled off Module
O PCIE AC coupled on Module
I PCIE AC coupled off Module
O PCIE
I/O PU/PD Comment
I/O 3.3V Chipset has internal pull-up
O 3.3V
I 3.3V Platform has internal PU
I/O OD PU 8.2k
3.3V 3.3V
O 3.3V
I/O PU/PD Comment
I/O USB 1.1/ 2.0 compliant
3.3VSB
Express-BD7
15