Evaluation Board Connectors - Analog Devices EVAL-ADAQ23875FMCZ User Manual

EVAL-ADAQ23875FMCZ

EVALUATION BOARD CONNECTORS

The functional descriptions for all the connectors (including a
160-pin FMC connector used to interface with the SDP-H1) used
on the EVAL-ADAQ23875FMCZ are listed in Table 2 and
Table 3, respectively.
Table 3. On-Board Connectors
Connector
J1
J2
J3
J4
VIN+
VIN−
+3P3V
P5
Table 4. 160-Pin FMC Connector (P5) Details
Signals
OSC_CLK+
OSC_CLK−
CLK±
CLK−
DCO+
DCO−
FPGA_CNV+
FPGA_CNV−
DA±
DB±
+3P3V_FMC
SCL
SDA
GA0
GA1
3P3VAUX
PG_C2M
CNV_EN
1 User defined signals with a P suffix can be used as the positive pin of the differential pair. User defined signals with an N suffix can be used as the negative pin of the
differential pair. For further information, see the VITA 57 specification.
2 User defined signals with a CC suffix are the preferred signal lines on which to transmit clock signals from the controller board to the daughter board. These signal lines are
connected to global clock lines on the FPGA, but they can also be used to carry any other user defined signal. For further information, see the VITA 57 specification.
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User Guide
Function
CLKIN input
EXT_CNV-
External CLK input
EXT_CNV+
Analog input V+
Analog input V−
External power supply
SDP-H1 FMC connector
Function
100 MHz low jitter positive line of differential pair for carrying clock signals from the daughter board.
100 MHz low jitter negative line of differential pair for carrying clock signals from the daughter board.
µModule CLK input signals connected to FPGA Bank 2.
µModule CLK input signals connected to FPGA Bank 2.
Positive line of differential pair for carrying clock signals from the daughter board.
Negative line of differential pair for carrying clock signals from the daughter board.
User defined signals connected to FPGA Bank 2.
User defined signals connected to FPGA Bank 2.
User defined signals connected to FPGA Bank 2.
User defined signals connected to FPGA Bank 2.
3.3 V (3 A) power supply to daughter board.
I 2 C clock line for reading FMC EEPROM.
I C data line for reading FMC EEPROM.
2
I 2 C geographical Address 0. Must be connected to Address Pin A1 of the FMC EEPROM.
I 2 C geographical Address 1. Must be connected to Address Pin A0 of the FMC EEPROM.
3.3 V (20 mA) power supply for powering only the FMC EEPROM.
Active high signal indicating that the 12P0V, 3P3V, and VADJ power supplies are turned on.
User defined signals connected to FPGA Bank 2.
There are several test points and single in line (SIL) headers on
the EVAL-ADAQ23875FMCZ. These test points provide easy
access to on-board signals for troubleshooting and evaluation
purposes.
1, 2
1, 2
1, 2
1, 2
1
1
1
Rev. 0 | Page 5 of 26
UG-1896