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7.
Troubleshooting and Recommendations
7.1
Errata
7.1.1
Impedance Mismatch on Revision C of the SAMA5D3x Main Board
There is an impedance mismatch on the revision C of the SAMA5D3x main board, impacting the clock signal of the
Ethernet PHY chip (MN20, KSZ8051RNL).This leads to a non-optimal data transmission on the ETH1 channel (J24), with
timeouts and retrials occurring from time to time.
Resolution:
Add a line termination on signal PC7.Connect PC7 to ground through a 200 Ohm resistor in series
with a 100pF ceramic capacitor. The connection point must be done at Pin 19 of Connector J2.
Figure 7-1
Figure 7-1.
Fixing An Impedance Mismatch on the Revision C of the SAMA5D3x Main Board
shows how and where to apply the fix.
SAMA5D3x-EK User Guide [USER GUIDE]
120
11180B–ATARM–29-Oct-13
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