Cpu Feature; Dram Configuration - JETWAY HA03 User Manual

3-11-2 CPU Feature

Virtualization
AMD K8 Cool & Quiet Control
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values
3-11-3

DRAM Configuration

DRAM Latency
RAS to CAS R/W Delay
Row Precharge Time
Minimum RAS Active Time
DRAM Command Rate
CKE base Power dowe mode
CKE BASED Powerdown
Memclock tri-slating
Memclock Hole Remapping
Auto optimize Bottom10
*Bottom of 【 31 ： 24 】 10 space
DDRII Timing Item
* Tw Tr Command delay
* Trfc 0 for DIMM 0
* Trfc 1 for DIMM 1
* Trfc 2 for DIMM 2
* Trfc 3 for DIMM 3
* (Twr) write Recovery Time
* (Trtp) Precharge Time
* (Trc) Row Cycle Time
* (Trrd) RAS# to CAS# Delay
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values
CAS # Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: Auto,3, 4 and 5.
RAS-to-CAS Delay
This field let's you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in
the system.
Row Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
Phoenix – AwardBIOS CMOS Setup Utility
CPU Feature
Enabled
Disabled
F6:Fail-safe Defaults
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Timing Settings
F6:Optimized Defaults
Menu Level >
F7:Optimized Defaults
Auto
Auto
Auto
Auto
Menu Level >>
2T
Disabled
per channel
Disabled
Enabled
Enabled
DO
Disabled
3 bus clock
75ns
75ns
75ns
75ns
6 bus clock
3 clocks
26 bus clock
5 clocks
F7:Standard Defaults
37
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