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V850ES/FE3-L uPD70F3611
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Manuals and User Guides for Renesas V850ES/FE3-L uPD70F3611. We have
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Renesas V850ES/FE3-L uPD70F3611 manual available for free PDF download: User Manual
Renesas V850ES/FE3-L uPD70F3611 User Manual (753 pages)
32-bit Single-Chip
Brand:
Renesas
| Category:
Microcontrollers
| Size: 14.99 MB
Table of Contents
Table of Contents
7
Chapter 1 Introduction
17
General
17
Features Summary
18
Description
21
Internal Units
23
Structure of the Manual
24
Ordering Information
25
V850ES/FE3-L Ordering Information
25
V850ES/FF3-L Ordering Information
27
V850ES/FG3-L Ordering Information
28
Chapter 2 Pin Functions
29
Overview
29
Description
30
Terms
32
Noise Elimination
32
Port Group Configuration Registers
33
Overview
33
Pin Function Configuration
34
Pin Data Input/Output
40
Configuration of Pull-Up Resistors
42
Open Drain Configuration
43
Port Buffers Diagrams
44
Port Type Diagrams
47
Port Type C
47
Port Type C-U
47
Port Type D0
48
Port Type D0-U
48
Port Type D1
49
Port Type D1-U
49
Port Type D1-UI
50
Port Type D3-UI
51
Port Type D1A
52
Port Type D1O1-UI
53
Port Type D2
54
Port Type E01-U
55
Port Type E10-U
56
Port Type E10-UI
57
Port Type E11-U
58
Port Type E11-UI
59
Port Type E21-U
60
Port Type Ex0-U
61
Port Type Ex1-U
62
Port Type Ex1-UI
63
Port Type Ex2-U
64
Port Type F010X-U
65
Port Type F010X-UI
66
Port Type F100X-U
67
Port Type F1010-U
68
Port Type F101X-U
69
Port Type F1100O0-U
70
Port Type F1100O1-U
71
Port Type F1100-U
72
Port Type F1110-UI
73
Port Type F113X-UI
74
Port Type F1X10-UI
75
Port Type F3X1X-UI
76
Port Type F1Xx0O1-U
77
Port Type Fx010-U
78
Port Type Fx01X-U
79
Port Type Fx103-UI
80
Port Type Fx10X-U
81
Port Type Fx10X-UI
82
Port Type Fx110-U
83
Port Type Fx120-UFI
84
Port Type Fx123-UFI
85
Port Type Fx12X-UFI
86
Port Type Fx13X-U
87
Port Type Fx210-U
88
Port Type Fx2X0-U
89
Port Type Fxx10-U
90
Port Type Fxx1X-U
91
Port Type Fxx2X-U
92
Port Group Configuration
93
Port Group Configuration Lists
93
Alphabetic Pin Function List
96
Port Group 0
100
Port Group 1 (V850ES/FG3, V850ES/FJ3, V850ES/FK3)
102
Port Group 3
103
Port Group 4
105
Port Group 5
106
Port Group 7
107
Port Group 9
109
Port Group CM
112
Port Group CS (V850ES/FF3-L, V850ES/FG3-L)
113
Port Group CT (V850ES/FF3-L, V850ES/FG3-L)
114
Port Group DL
115
Noise Elimination
116
Analog Filtered Inputs
116
Digitally Filtered Inputs
117
Pin Functions in Reset and Power Save Modes
120
Recommended Connection of Unused Pins
121
Package Pins Assignment
122
V850ES/FE3-L Package Pins Assignment
122
V850ES/FF3-L Package Pins Assignment
123
V850ES/FG3 Package Pins Assignment
124
Chapter 3 CPU System Functions
125
Overview
125
Description
126
CPU Register Set
127
General Purpose Registers (R0 to R31)
128
System Register Set
129
Operation Modes
136
Normal Operation Mode
136
Flash Programming Mode
136
On-Chip Debug Mode
136
Address Space
137
CPU Address Space and Physical Address Space
137
Program and Data Space
139
Memory
141
Memory Areas
141
Recommended Use of Data Address Space
144
Write Protected Registers
145
Write Protection Control Registers
147
Chapter 4 Clock Generator
148
Overview
148
Description
149
Clock Monitor
152
Power Save Modes Overview
153
Start Conditions
154
Clock Generator Registers
155
General Clock Generator Registers
157
PLL Control Registers
167
Stand-By Control Registers
170
Prescaler3 Control Registers
172
Clock Monitor Control Registers
173
Selector Control Registers
174
Option Bytes
177
Option Byte 0000 007A H
178
Option Byte 0000 007B H
179
Clock Generator Operation
180
Overview of Clock Operation Control Settings
180
Operation State Transitions
181
Power Save Modes Description
184
Available Clocks in Power Save Modes
200
Power Save Mode Activation
202
Controlling the PLL
204
Watch Dog Timer Clock
204
CLKOUT Function
204
Operation of Prescaler3
205
Operation of the Clock Monitor
206
Chapter 5 Interrupt Controller (INTC)
209
Features
209
Non-Maskable Interrupts
213
Operation
216
Restore
217
Non-Maskable Interrupt Status Flag (NP)
218
NMI Control
218
Maskable Interrupts
219
Operation
219
Restore
221
Priorities of Maskable Interrupts
222
Xxicn - Maskable Interrupt Control Registers
226
Imrm - Interrupt Mask Registers
229
ISPR - In-Service Priority Register
232
Maskable Interrupt Status Flag (ID)
233
External Maskable Interrupts
233
External Interrupts Edge Detection Configuration
233
Software Exception
239
Operation
239
Restore
240
Exception Status Flag (EP)
241
Exception Trap
242
Illegal Opcode Definition
242
Debug Trap
243
Multiple Interrupt Processing Control
245
Interrupt Response Time
247
Periods in Which Interrupts Are Not Acknowledged
248
Chapter 6 Key Interrupt Function
249
Function
249
Control Register
250
Cautions
250
Chapter 7 Flash Memory
251
Code Flash Memory Overview
252
Code Flash Memory Features
252
Code Flash Memory Mapping
253
Code Flash Memory Functional Outline
255
Code Flash Memory Erasure and Rewrite
258
Flash Programming with Flash Programmer
259
Programming Environment
259
Communication Mode
260
Pin Connection with Flash Programmer PG-FP5
262
Flash Memory Programming Control
264
Code Flash Self-Programming
269
Self-Programming Enable
270
Self-Programming Library Functions
270
Secure Self-Programming (Boot Cluster Swapping)
271
Interrupt Handling During Flash Self-Programming
275
Variable Reset Vector
276
Flash Mask Options
277
Device Information
279
PRDSELH Register - Product Selection Code Register
279
Chapter 8 Data Protection and Security
280
Overview
280
N-Wire Debug Interface Protection
280
Flash Programmer and Self-Programming Protection
282
Chapter 9 Bus Control Unit (BCU)
285
Description
285
Peripheral I/O Area
286
NPB Access Timing
288
Bus Properties
289
Boundary Operation Conditions
289
Registers
291
Chapter 10 16-Bit Timer/Event Counter AA
294
Features
294
Function Outline
295
Configuration
295
Input Selection Registers
301
Control Registers
303
Operation
316
Anytime Write and Reload
317
Interval Timer Mode (Taanmd2 to Taanmd0 = 000 B )
321
External Event Counter Mode (Taanmd2 to Taanmd0 = 001 B )
325
External Trigger Pulse Mode (Taanmd2 to Taanmd0 = 010 B )
329
One-Shot Pulse Mode (Taanmd2 to Taanmd0 = 011 B )
332
PWM Mode (Taanmd2 to Taanmd0 = 100 B )
335
Free-Running Mode (Taanmd2 to Taanmd0 = 101 B )
340
Pulse Width Measurement Mode (Taanmd2 to Taanmd0 = 110B)346
346
32-Bit Capture in Free-Running Cascade Mode
353
Capture Operation on Delayed Input Clock
358
Chapter 11 16-Bit Interval Timer M
359
Features
359
Configuration
360
Timer M Registers
361
Operation
363
Interval Timer Mode
363
Cautions
364
Chapter 12 Timer AA Synchronous Operation
365
Chapter 13 Watch Timer Functions
367
Functions
367
Configuration
368
Control Registers
369
Operation
371
Operation as Watch Timer
371
Operation as Interval Timer
371
Cautions
372
Chapter 14 Watchdog Timer 2
373
Functions
373
Configuration
374
Control Registers
375
Watchdog Timer Operation
378
Watchdog Timer Operation in Power Save Mode
378
Chapter 15 Asynchronous Serial Interface (UARTD)
379
Features
380
Configuration
381
UARTD Registers
384
Interrupt Request Signals
394
Operation
395
Data Format
395
SBF Transmission/Reception Format
397
SBF Transmission
399
SBF Reception
399
Data Consistency Check
401
UART Transmission
403
Continuous Transmission Procedure
404
UART Reception
406
Reception Errors
407
Parity Types and Operations
408
Receive Data Noise Filter
409
Baud Rate Generator
410
Cautions
417
Chapter 16 Clocked Serial Interface (CSIB)
418
Features
418
Configuration
419
CSIB Control Registers
421
Operation
428
Single Transfer Mode (Master Mode, Transmission/Reception Mode)
428
Single Transfer Mode (Master Mode, Reception Mode)
430
Continuous Mode (Master Mode, Transmission/Reception Mode)
431
Continuous Mode (Master Mode, Reception Mode)
433
Continuous Reception Mode (Error)
434
Continuous Mode (Slave Mode, Transmission/Reception Mode)
435
Continuous Mode (Slave Mode, Reception Mode)
437
Clock Timing
438
Output Pins
440
Operation Flow
441
Chapter 17 I 2 C Bus (IIC)
448
Features
448
I 2 C Pin Configuration
448
Configuration
449
IIC Registers
453
I 2 C Bus Mode Functions
470
Pin Functions
470
I 2 C Bus Definitions and Control Methods
471
Start Condition
471
Addresses
472
Transfer Direction Specification
473
Acknowledge Signal (ACK)
473
Stop Condition
474
Wait Signal (WAIT)
475
C Interrupt Request Signals (Intiicn)
477
Master Device Operation
477
Slave Device Operation
480
Slave Device Operation (When Receiving Extension Code)
484
Operation Without Communication
488
Arbitration Loss Operation (Operation as Slave after Arbitration Loss)
488
Operation When Arbitration Loss Occurs
490
Interrupt Request Signal (Intiicn)
495
Address Match Detection Method
496
Error Detection
496
Extension Code
497
Arbitration
498
Wakeup Function
499
Cautions
500
Communication Operations
501
Master Operation 1
501
Master Operation 2
502
Slave Operation
503
Timing of Data Communication
507
Chapter 18 CAN Controller (CAN)
514
Features
515
Overview of Functions
516
Configuration
517
CAN Protocol
518
Frame Format
518
Frame Types
519
Data Frame and Remote Frame
519
Error Frame
526
Overload Frame
527
Functions
528
Determining Bus Priority
528
Bit Stuffing
528
Multi Masters
529
Multi Cast
529
CAN Sleep Mode/Can Stop Mode Function
529
Error Control Function
529
Baud Rate Control Function
536
Connection with Target System
539
Internal Registers of CAN Controller
540
CAN Module Register and Message Buffer Addresses
540
CAN Controller Configuration
541
CAN Registers Overview
542
CAN3 Register Bit Configuration
548
Bit Set/Clear Function
551
Control Registers
553
CAN Controller Initialization
589
Initialization of CAN Module
589
Initialization of Message Buffer
589
Redefinition of Message Buffer
589
Transition from Initialization Mode to Operation Mode
591
Resetting Error Counter Cnerc of CAN Module
592
Message Reception
593
Receive Data Read
594
Receive History List Function
595
Mask Function
597
Multi Buffer Receive Block Function
598
Remote Frame Reception
599
Message Transmission
600
Transmit History List Function
602
Automatic Block Transmission (ABT)
604
Transmission Abort Process
606
Remote Frame Transmission
607
Power Saving Modes
608
CAN Sleep Mode
608
CAN Stop Mode
611
Example of Using Power Saving Modes
612
Interrupt Function
613
Diagnosis Functions and Special Operational Modes
614
Receive-Only Mode
614
Single-Shot Mode
615
Self-Test Mode
616
Receive/Transmit Operation in each Operation Mode
617
Time Stamp Function
618
Baud Rate Settings
619
Baud Rate Setting Conditions
619
Representative Examples of Baud Rate Settings
623
Operation of CAN Controller
627
Chapter 19 A/D Converter (ADC)
653
Functions
653
Configuration
655
ADC Registers
657
Operation
669
Basic Operation
669
Trigger Mode
670
Operation Modes
672
Power-Fail Compare Mode
677
Cautions
683
How to Read A/D Converter Characteristics Table
685
Chapter 20 Power Supply Scheme
690
Overview
690
Description
691
On-Chip Voltage Regulators
692
Chapter 21 Reset
693
Overview
693
General Reset Performance
693
Reset at Power-On
696
External RESET
698
Reset by Watchdog Timer 2
699
Reset by Clock Monitor
699
Reset by Low-Voltage Detector
699
Reset Registers
700
Chapter 22 Low-Voltage Detector
701
Functions
701
Configuration
702
Registers
703
Operation
707
Reset Generation from LVI (LVIM.LVIMD = 1)
707
Interrupt Generation from LVI (LVIM.LVIMD = 0)
708
Disabling the LVI Operation
709
RAM Retention Voltage Detection Operation
710
Chapter 23 On-Chip Debug Unit
711
Functional Outline
711
Debug Functions
711
Controlling the N-Wire Interface
714
N-Wire Enabling Methods
716
Starting Normal Operation after RESET and RESPOC
716
Starting Debugger after RESET and RESPOC
716
N-Wire Activation by RESET Pin
717
Connection to N-Wire Emulator
718
KEL Connector
718
Restrictions and Cautions on On-Chip Debug Function
722
Appendix A Special Function Registers
723
CAN Registers
723
Other Special Function Registers
725
Appendix B Registers Access Times
734
Timer AA
735
Timer M
736
Watchdog Timer 2
737
A/D Converter
737
I2C Bus
738
Asynchronous Serial Interface (UARTD)
738
Clocked Serial Interface (CSIB)
738
CAN Controller
739
All Other Registers
739
Appendix C Differences between Fx3-L Andfx3
740
Revision History
741
Index
743
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