Quectel EM05-G Hardware Design page 43

PCM_CLK
PCM_SYNC
PCM_DOUT
PCM_DIN
The following table shows the pin definition of PCM interface which can be applied to audio codec design.
Table 12: Pin Definition of PCM Interface
Pin No. Pin Name
20 PCM_CLK
22 PCM_DIN
24 PCM_DOUT
28 PCM_SYNC
The clock and mode can be configured by AT command, and the default configuration is master mode
using short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. See
document [3] for details about AT+QDAI.
EM05-G_Hardware_Design
1 2
MSB
MSB
Figure 20: Auxiliary Mode Timing
I/O Description
DIO, PD PCM clock
DI, PD PCM data input
DO, PD PCM data output
DIO, PD PCM data frame sync
LTE Standard Module Series
125 μs
31 32
LSB
LSB
DC Characteristics
1.8 V
1.8 V
1.8 V
1.8 V
EM05-G Hardware Design
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