Allegro MicroSystems A8600 Manual page 8

A8600
VIN3
CLK180
FB4
TSDH
VREG POR
EN
UVLO
UVLO
LX4
860mV
740mV
Figure 3. Detailed functional block diagram for SW4
Quadruple Output Regulator with Two High-Side Switches,
OSCILLATOR
IF FB 4<0.4V then F / 2
IF HICCUP 4= 1 then F / 4
T
E LS E F O FF,M IN
SLOPE
COMP
I
ERROR
FB4
800mV
REF
400mV
B OOT4 – LX 4
MONITOR &
BOOT 4
COUNTERS
7x B OOTx OV or
LX4
30x B OOTx UV
I
SENSE4
COMPARATOR
COMP4
M AX
& COUNTER
2.3V
SS4 > 2.3V E NA B LE
COUNTE R
0.3V
FB4 > 0.3V
0 = 30 c ounts
1 = 118 c ounts
UVLO4
↑
ON
↓
OF F
LX4 or
LG2
FA ULTS
SS4 < 0.2V
0.2V
FB4 OV
FB4 UV
BU/ACC Voltage Detectors, and Mute Delay
400mV
I
SENSE4
G
PWM
DOMINA NT
COMPARATOR
AMP
PWM4
RST
CLAMP COMP4
BOOT
S Q
OC4
R Q
RE S E T
DOMINA NT
S Q
R Q
ILIM
ON
CSA
UP P E R FE T ON:
Q = 1 & T = 0
O FF,M IN
RE S E T
UP P E R FE T OFF:
FB 4 OV or
1x OC4 = 1 or
Q
S Q
1x B OOT4 UV or
S S INIT4 =1 or
HICCUP4 = 1
R Q Q
OV E RLA P
LOWE R FE T ON:
Q = 1 & T = 1 or
O FF, M IN
B OOT4 UV & T = 1
O FF, M IN
LOWE R FE T OFF :
S S INIT4 = 1 or
HICCUP4 = 1
M AX
ISS ISS
SU4 HIC4
HICCUP4
SSINIT 4
S Q
R Q
DE-
GLITCH
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A8600
BOOT 4
CSP
CSN
HG4
LX4
GA TE
DRIV E R
NON- VIN 3
LG4
PGND
COMP4
SS4
1K 5K
POK 4
8