Allegro MicroSystems A8600 Manual page 30

A8600
to VINS) through the switches. S1 and S2 are simultaneously
controlled on or off by the ENS pin. The A8600 contains an inter-
nal charge pump to provide gate drive to S1 and S2.
If OUT1 or OUT2 is pulled down relatively slowly by a heavy
load, the switch will protect itself by limiting its current to about
350 mA . If the output of S1 or S2 drops below 8 V, the switch
DC
will begin to foldback the current. At 0 V output, each switch
typically delivers only 100 mA. However if OUT1 or OUT2 is
very quickly shorted to ground, the switch will allow a relatively
high peak current, approximately 800 mA(peak) at V
for a short time. This scheme allows for minimal power dissipa-
tion while allowing OUT1/OUT2 startup with capacitive loads
up to 1 µF. For thermal reasons, if VINS exceeds approximately
18.3 V, both S1 and S2 are turned off.
Figure 15 shows the typical DC fold back characteristics of the
high-side switches. Figure 16 shows a high-side switch turn-
ing on with V = 12 V and a 40 Ω/22 µF load. In figure 16,
INS
notice the switch is starting with foldback limiting, allowing
only 100 mA when V = 0 V, increasing the current to about
OUTx
400 mA when V exceeds 5 V, and providing full output
OUTx
voltage with a 300 mA load. Without foldback control, the switch
would have allowed an extremely high peak current due to the
20
15
10
5
0
0 50 100
Current Limit (mA)
Figure 15. Typical DC current fold back versus V
Quadruple Output Regulator with Two High-Side Switches,
INS
150 200 250 300 350
of S1 and S2
OUTx
BU/ACC Voltage Detectors, and Mute Delay
capacitive load (> 20 A) and the A8600 may have been damaged
or caused some other system level malfunction, such as UVLO
of the entire IC.
In some applications, S1 and S2 are connected to a wiring har-
ness to supply a remote load at a relatively long distance from
the A8600. The wiring harness will introduce significant series
inductance (4 to 6 µH) between the OUTx pin and the actual
load. This forms an LC tank circuit with very low resistance. If
the load is short circuited to ground, the OUTx pin will transi-
= 18 V, tion or ring below ground for a short time. To protect the A8600,
Allegro strongly recommends the use of a 1 A, 30 V (min) diode,
as shown in the Typical Application diagram, to help clamp the
negative voltage at the OUT1/OUT2 pins. Preferably, this clamp
diode would be a Schottky type.
For most applications, the VINS pin will share a common input
node with the buck switcher VIN1/2/3/4 pins, as shown in
figure 17. In this configuration, the VINs pin is protected from
negative transients (such as during a Field Decay test) by two
series diodes, the MOSFET body diodes and the external, asyn-
chronous Schottky diodes, DSW1 through DSW4 . Depending on
the application, it may be necessary to isolate the VINS pin from
the switching noise on the VIN1/2/3/4 pins.
C1
V
ENS
C2
V
OUTx
100 mA
C3
I
400
OUTx
Figure 16. S1/S2 OUTx turning on with a load of 40 Ω and 22 µF; shows
V (ch1, 5 V/div.), V
ENS
t = 500 µs/div.
400 mA
300 mA
t
(ch2, 5 V/div.), I (ch3, 200 mA/div.),
OUTx OUTx
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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