Allegro MicroSystems A8600 Manual page 51

A8600
9.00 ±0.20 7.00 ±0.20
48
A
1 2
48X
0.08 C
0.22 ±0.05
Quadruple Output Regulator with Two High-Side Switches,
Package Outline Drawing
Package JP, 48-Pin LQFP
9.00 ±0.20
7.00 ±0.20
B
5.00
5.00
0.50
0.10 ±0.05
BU/ACC Voltage Detectors, and Mute Delay
7º
4° ±4
0º
+0.05
0.15
–0.06
0.60 ±0.15
(1.00)
48
0.25
SEATING PLANE
GAGE PLANE
C
SEATING
PLANE
For Reference Only
(reference JEDEC MS-026 BBCHD)
1.60 MAX
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
1.40 ±0.05
Exact case and lead configuration at supplier discretion within limits shown
Terminal #1 mark area
A
B Exposed thermal pad (bottom surface)
Reference land pattern layout (reference IPC7351
QFP50P900X900X160-48M); adjust as necessary to meet
application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
0.30
1.70
C
1 2
5.00
8.60
C PCB Layout Reference View
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
0.50
5.00 8.60
51