Bu And Acc Detectors And Mute Output; Power Ok (Pok) Output - Allegro MicroSystems A8600 Manual

A8600
One method to accomplish this is to add an additional LC filter,
as shown in figure 18. In this configuration the body diode
and external Schottky diode from the buck swtichers no longer
protect the VINS pin from negative voltage transients. If the
VINS pin is isolated in any way, Allegro recommends adding a
Schottky diode, DVINS, at the VINS pin as shown in figure 18.
There are two levels of thermal protection in the A8600. A
detailed description of these two levels, how they affect the
operation of S1 and S2, and how they must be reset is provided in
the Protections Features section of this data sheet.
See the Timing Diagrams section for operation of the high-side
switches during current limit and high temperature.

BU and ACC Detectors and MUTE Output

The A8600 includes two relatively simple comparators to monitor
both V /V and V /V
BAT IN BAT
switch. The BU comparator monitors V
The ACC comparator monitors the ignition switch at the ACCI
pin. Both comparators have an internal reference of 1.205 V at
their negative pins. Therefore, a resistor divider must be used to
set the BU and ACC thresholds to something higher than 1.205 V,
as shown in the Typical Application diagram. Also, if hysteresis is
necessary, this must be done with an external resistor from BUO
to BUI and ACCO to ACCI, as shown in the Typical Application
diagram.
It should be noted that the ACC comparator also controls the
mode of SW1. If the EN/SYNC and ACCI inputs are low, SW1
will enter Low IQ PFM mode after 2048 PWM cycles. If ACCI
VBAT
Figure 17. VINS pin connected directly to VIN1/2/3/4 pins
Quadruple Output Regulator with Two High-Side Switches,
applied through a key-type ignition
IN
/V at the BUI pin.
BAT IN
VINs
VIN1 - VIN4
BODY
DIODE
SCHOTTKY
BU/ACC Voltage Detectors, and Mute Delay
is high, it will immediately force SW1 into normal, high-current
PWM mode.
See the Timing Diagrams section for operation of the BU and
ACC detectors.
The A8600 has an open drain, active low MUTE output with a
programmable on-time. The MUTE output is an open drain out-
put, therefore an external pull-up resistor must be used as shown
in the Typical Application Circuit diagram. The MUTE on-time
is set by a counter and a capacitor from the CTMR pin to ground.
Basically, any time the BU comparator changes state the MUTE
output is pulled low while the CTMR pin transitions 10 times
between V and V
CTMRH
state before the counter reaches 10, the counter will be reset to 0
and the MUTE time extended. The BU comparator has a de-
glitch filter, so any fast transient on BUI lasting less than 16 µs
(typ) will be ignored and a false MUTE will not occur. T
T do not affect the MUTE output.
TSDH
See Timing Diagrams section for operation of the MUTE and
CTMR pins in conjunction with the BU detector.

Power OK (POK) Output

The A8600 has a Power OK (POK) output. The POK output is
an open drain output, so an external pull-up resistor must be used
as shown in the Typical Application Circuit diagram. The POK
output is pulled low if either an under- or overvoltage condition
occurs at FB2, FB3, or FB4. SW1 is an always-on regulator, so it
does not help control POK. The typical POK thresholds are set at
±60 mV (±7.5% of 800 mV).
VBAT
Figure 18. VINS isolated from VIN1/2/3/4, so the addition of D
required
. If the BU comparator changes
CTMRL
VINs
D_VINs
VIN1 - VIN4
BODY
DIODE
SCHOTTKY
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
and
TSDL
is
VINS
31