Power Dissipation And Thermal Calculations - Allegro MicroSystems A8600 Manual

A8600
2) Calculate the RZx resistor value to set the required system
bandwidth (f ):
C
V
R f
SWx
=
×
Zx C
V
FBx
3) Determine the frequency of the pole (f
R by using equation 30 (repeated here):
LOAD
f
=
P1x
2� R
×
4) Calculate a range of values for the CZx capacitor:
4
C
<
f
2� R
× ×
Zx Cx
To maximize system stability (that is, to have the most gain
margin), use a higher value of CZ
recovery time, at the expense of some phase margin, use a lower
value of CZ . Figure 28 shows the output voltage recovery time
X
due to a 1A load transient for the system shown in figure 27
(f = 3.8 kHz, 66° phase margin) and a system with f
Z2
crossover frequency, or 9 kHz. The system with f
has 57° of phase margin but recovers about twice as fast as the
other system.
5) Calculate the frequency of the ESR zero (f
output capacitor(s) by using equation 31 (repeated here):
f
=
Z1x
2� ESRx
×
5a) If f is at least 1 decade higher than the target crossover
Z1
frequency (f ) then f can be ignored. This is usually the case
C Z1
for a design using ceramic output capacitors. Use equation 35
to calculate the value of CPx by setting f
f / 2, whichever is higher.
SW
5b) Conversely, if f is near or below the target crossover fre-
Z1
quency (f ) then use equation 35 to calculate the value of CPx by
C
setting f equal to f . This is usually the case for a design using
P3 Z1
high ESR electrolytic output capacitors.
Quadruple Output Regulator with Two High-Side Switches,
2� C
×
SWx
×
g g
×
mPOWERx mx
) formed by C
P1
1
C
×
SWx
LOAD
1
<
Zx
2� 1.5 f
R
× × ×
Zx P1x
. To optimize transient
X
Z2
at 9 kHz
Z2
) formed by the
Z1
1
C
×
SWx
to either 5 × f
P3
BU/ACC Voltage Detectors, and Mute Delay

Power Dissipation and Thermal Calculations

The power dissipated in the A8600 is the sum of the power dissi-
(36) pated from the V
to the switching of the internal power MOSFETs (P
and
power dissipated due to the rms current being conducted by the
SWx
internal MOSFET (P
internal gate drivers (P
due to the rms current being conducted by the two high-side
switches (P
S1/S2
The power dissipated from the V
lated using the following equation:
P
INTOTAL
(34)
where V is the input voltage, I
INx
drawn by the A8600 (nominally 7.5 mA), V
gate drive voltage (typically 5 V), Q
gate charge (approximately 2.5 nC), Q
gate charge for SW4, and f
at 1 / the
The power dissipated by the internal high-side MOSFET while it
4
is switching can be calculated using the following equation:
V
P
≥
SW1/2/3
where V is the input voltage, I
INx
rent, f is the PWM switching frequency, and t
SWx
rise and fall times measured at the V
fall times at the V
nents and PCB layout so each design should be measured at full
load. Approximate values for both t
The power dissipated by the internal high-side MOSFETs while
they are conducting can be calculated using the following equa-
or
tion:
C
P
=
COND1/2/3
=
supply current (P ), the power dissipated due
IN IN
), the power dissipated by the four
COND1/2/3
), and the power dissipated
DRIVER1/2/3/4
).
supply current can be calcu-
IN
= V × I – V
+ (V
INx Q INx GSx
× (3 × Q + Q ) × f
G G4 SW
is the input quiescent current
Q
is the internal MOSFET
G
is the external MOSFET
G4
is the PWM switching frequency.
SW
I (t + t
× ×
IN1/2/3 SW1/2/3x r f
2
is the regulator output cur-
SWx
node. The exact rise and
LXx
node will depend on the external compo-
SWx
and t
r f
2
I R
×
rms(FET)1/2/3 DS(on)HS1/2/3
V +V
2
SW1/2/3 f1/2/3
I
×
LSW1/2/3
V
+V
IN1/2/3 f1/2/3
R
×
DS(on)HS1/2/3
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
), the
SW1/2/3
)
(35)
is the MOSFET
GS
) f
×
SW
(36)
and t are the
r f
range from 5 to 10 ns.
2
∆I
L1/2/3
+
12
(37)
44