A8600
In PFM mode, SW1 operates with a switching frequency that
depends on the load condition. The average current drawn from
the input supply depends primarily on the load and how often the
A8600 must wake up to maintain regulation.
In PFM mode, a comparator monitors the voltage at FB1. If the
voltage at FB1 is above approximately 800 mV, the A8600 will
remain in keep-alive mode and draw extremely low current from
the input supply.
If the voltage at the FB1 pin drops below approximately 800 mV,
the A8600 will wake up, and after a delay of approximately 2 µs
for the IC to fully power-up, turn on the upper MOSFET. V
rises at a rate dependent on the input voltage, inductor value, and
output capacitance.
The upper MOSFET is turned off when either: (1) the upper
MOSFET (that is, the output inductor) current reaches approxi-
mately 800 mA, or (2) the upper MOSFET has been on for
approximately 4 µs. After the upper MOSFET is turned off, the
A8600 will delay approximately 300 ns and either: (1) turn the
MOSFET on again if the voltage at FB1 is still below 800 mV or
(2) return to the extremely low current keep-alive mode. Figures
11 and 12 demonstrate PFM mode operation for a light load and
an increased load, respectively.
In PFM mode the following faults are detected: a missing
asynchronous diode, an open or shorted boot capacitor, V
shorted to ground, or LX1 shorted to ground. As described in the
previous section for PWM mode, if any of these faults occur the
3.3 V
V
SW1
V
LX1
C2
800 mA
I
LX1
C3
C1
Figure 11. SW1 PFM operation at V
50 mA load, LX1 turns on once every 26 µs to regulate V
(ch1, 100 mV/div.), V
(ch2, 5 V/div.), I
LX1
t = 5 µs/div.
Quadruple Output Regulator with Two High-Side Switches,
SW1
t
= 12 V, V
= 3.3 V, V
IN1
SW1
SW1
; shows V
SW1
(ch3, 500 mA/div.),
LX1
BU/ACC Voltage Detectors, and Mute Delay
A8600 will transition from Low IQ PFM mode to Low IP PWM
mode, and operate at 50% of the normal PWM current limit. See
the Timing Diagrams section for operation of SW1 in Low IQ
PFM mode.
In PFM mode the A8600 dissipates very little power, so the ther-
mal monitoring circuit (TSD) is not required and is disabled to
minimize the quiescent current.
Soft Start (Startup) and Inrush Current
Control
SW1
Inrush currents to the 4 switchers are controlled by the soft start
function. When the A8600 is enabled and all faults are cleared,
the Soft Start pin, SSx, will source I
Soft Start capacitor, CSSx, will ramp upward from 0 V. When
the voltage at the Soft Start pin exceeds approximately 400 mV,
the error amplifier slews its output voltage above the PWM
Ramp Offset (V
PWMOFFSETx
MOSFETs will begin switching. As shown in figure 13, there is
a delay (t
) between when the Enable pin transitions high and
dSSx
the combination of the soft start voltage exceeding 400 mV and
the error amplifier slewing its output enough to initiate PWM
switching.
Once the A8600 begins switching, the error amplifier will
regulate the voltage at the FBx pin to the SSx pin voltage, minus
approximately 400 mV. During the active portion of soft start, the
3.3 V
V
SW1
V
LX1
C2
I
LX1
C3
C1
=
Figure 12. SW1 PFM operation at V
120 mA load, LX1 turns on twice every 18 µs to regulate V
SW1
V
(ch1, 100 mV/div.), V
SW1
t = 5 µs/div.
and the voltage on the
SSSUx
). At that instant, the upper and lower
t
≈ 300 ns
OFF
800 mA
t
= 12 V, V
IN1
SW1
(ch2, 5 V/div.), I
(ch3, 500 mA/div.),
LX1
LX1
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
= 3.3 V, V
=
SW1
; shows
SW1
28
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