Typical Application Circuit - Allegro MicroSystems A8600 Manual

A8600
Top Level Functional Block Diagram and Typical Application Circuit
VBAT VBAT _FILT
2200
≈ 35 V
CP1
27 pF
CZ1
4.7 nF
CP2
27 pF
CZ2
2.2 nF
CP3
27 pF
CZ3
2.2 nF
5.0 V
To
microcontroller
CP4
Optional: POK
27 pF
to OUT2 short
protection for
microcontroller
CZ4
2.2 nF
Optional: ENS
to OUT1 for short
protection for
microcontroller
From
microcontroller
Optional: To
protect VINS
for Field Decay test
3 A
40V
ACC
Switch
60.4 kΩ
1%
60.4 kΩ
1%
22.1 kΩ
1%
475 kΩ
1%
78.7 kΩ
1%
A
Block active in Low IQ mode
B
Current will not flow from ACCI to BUI or any VINx pin
C Current will not flow from ACCO, BUO, MUTE, BIAS, VREG, FB1, POK, or OUTx to any VINx pin
D
SW4 lower FET must not cause V
Quadruple Output Regulator with Two High-Side Switches,
A8600
µF
COMP1
RZ1
18.7 kΩ
SS1
Bias
CSS1
Switch On
0.68 µF
VIN1
LDO
Off
BIAS >3.2V and
C
BIAS >LDO
OUT
VREG
1.0 µF
1.205V
Band REF
Gap
COMP2
RZ2
39.2 kΩ
SS2
CSS2
22 nF
VREG
POR
TSDH
S
TSD
R
TSDL
S Q
R
EN
S
VIN UVLO
S
COMP3
RZ3
18.7 kΩ
SS3
Oscillator
CSS3
180° Shift
22 nF
with
Synchronization
VREG
EN/SYNC
200 kΩ
C
POK
COMP4
RZ4
24.9 kΩ
SS4
CSS4
22 nF
POK2
POK3
POK4
GND
ENS
200 kΩ
3.70 V
VINS UVLO
+
–
VINS
215 mV
2 µA 2 µA
A
CTMR
1.205 V
CCTMR
0 .1 µF
50 kΩ
ACCI
≈
B 6.2 V
825 kΩ
1%
BUI
≈
1 MΩ B 6.2 V
1%
to decay during prebias startup
SW4
BU/ACC Voltage Detectors, and Mute Delay
VREG POR
A
COMP1 Switcher 1
(SW1)
SS1
Adjustable
Always-On
CLK0
V PWM/PFM
REG
Asynchronous
Buck Regulator
Delay
EN/PFM
2048↓
VREG POR
V
REGPORH
V
COMP2
REGPORL
SS2
Switcher 2
(SW2)
CLK180
Adjustable
EN PWM
Asynchronous
TSDH
Buck Regulator
POK2
Q
VREG POR
COMP3
SS3 Switcher 3
(SW3)
CLK0
Adjustable
EN PWM
Asynchronous
TSDH
Buck Regulator
Delay
POK3
15 ↓
VREG POR
COMP4
Switcher 4
SS4
(SW4)
CLK180 Adjustable
PWM
EN
Synchronous
TSDH
Buck Controller
POK4
High-Side Switch 1
(S1) with
Foldback Limiting
TSDL
1.0 Ω Total
Charge
High-Side Switch 2
Pump
(S2) with
Foldback Limiting
TSDL
1.0 Ω Total
TSDL
SET
RST
Mute
Logic
CHARGE
DONE
8 to 32 μs
De-glitch BU
CLEAN
PAD
C
BIAS
3.3 to 5.5 V
BOOT 1
VIN1
Optional: To
maintain V
BOOT1
CIN1
CBOOT1
during very
47 nF low V
BAT
150 mΩ
10µH
LSW1
LX1
CSW1
10 Ω DSW1
10pF
50µF
3 A
40 V
147 kΩ
FB1
R
FBA1
C
47 kΩ
R
FBB1
BOOT2
VIN2
VBAT _FILT
VIN2
CIN2
CBOOT2
47 nF
120 mΩ
LX2 LSW2 15 µH
LX2
CSW2
DSW2
10 Ω
50 µF
3 A
40 V
16.2 kΩ
FB2
R
FBA2
1.8 kΩ
R
FBB2
BOOT 3
VIN3
VBAT _FILT
VIN3
CIN3
CBOOT3
112 mΩ 47 nF
LX3
10 µH
LSW3
LX3
CSW3
DSW3
10 Ω
50µF
3 A
40 V
14.7 kΩ
FB3
R
4.7 kΩ
FBA3
R
VIN3 FBB3
BOOT 4
CSN
CSP
VBAT _FILT
CBOOT4
0.1 µF
LSW4
HG4
10 µH
Shoot-
50 kΩ
Through
LX4
Protec-
D DSW4
tion
3 A
LG4
40 V
50 kΩ
FB4
Schottky for SW4
1.8 kΩ
may be omitted for
PGND
very low current
system only
C
OUT1
1 µF
200 kΩ S1A
50 V
C
OUT2
1 µF Optional: MUTE
200 kΩ S1A
to VIN1 short
50 V
protection for
amplifier
MUTE
C
BU 3.3V
15 kΩ
BIAS
TC7S H14F
ACCO
1 µF
10 kΩ
C
BIAS
9.1 kΩ BU 3.3V
BUO
TC 7S H14F
C
1µF
4.7 kΩ
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
V
SW1
Adj 3.3 V
1.0 A
AVG
2.5 A
PEAK
V
SW2
Adj (8V)
1.0 A
AVG
2.5 A
PEAK
V
SW3
Adj (3.3 V)
2.0 A
AVG
2.5 A
PEAK
RS
15 m Ω
V
SW4
CSW4
Adj (5.7 V)
50 µF
2.5 A
AVG
4.0 A
11 kΩ PEAK
R
FBA4
R
FBB4
LOAD 1
LOAD 2
5.0V
Audio
Amplifier
To
microcontroller
To
microcontroller
6