Allegro MicroSystems A8600 Manual page 47

Quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay
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A8600
VIN3
Figure 28. Typical buck converter PCB layout, with critical paths and loops shown
Loop 1 (Red): At the instant Q3 turns on, the Schottky diode D3 (which is very capacitive), must be very quickly charged and shut off. The
spike of charging current must come from the input capacitors, CIN1/2/3. This spike of current is quite large and will be an EMI/EMC issue
if loop 1 is not minimized. Therefore, the input capacitors and Schottky diode D3 must be placed be on the same (top) layer, be located near
each other, and be grounded at virtually the same point on the PCB.
Loop 2 (Brown): When Q3 is off, free-wheeling inductor current must flow from ground through diode D3, into the output inductor, out to the
load and return via ground. While Q3 is off, the voltage on the output capacitors will decrease. The output capacitors and Schottky diode D3
must be placed on the same (top) layer, be located near each other, and be grounded at virtually the same point on the PCB.
Loop 3 (Blue): When Q3 is on, current flows from the input supply and input capacitors through the output inductor and into the load. At this
time the voltage on the output capacitors will increase.
Figure 29. Example PCB component placement and routing, example shows SW3
Quadruple Output Regulator with Two High-Side Switches,
Loop 3
Loop 1
LX3
Q3
CIN3
CIN2
CIN1
D3
Q3
VIN
GND
Loop 3
BU/ACC Voltage Detectors, and Mute Delay
Loop 2
...
LSW3
RSNUB3
(CSWx)
CO1
CSNUB3
...
Loop 1
Loop 2
(V
)
SW3
VOUT3
CO5
LOAD
LOAD
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
47

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