Functional Description; Overview; Reference Voltage; Pwm Switching Frequency - Allegro MicroSystems A8600 Manual

A8600

Overview

The A8600 is a highly sophisticated, multi-function IC that
incorporates all the control and protection circuitry necessary to
provide the power supply requirements of next generation car
audio and infotainment systems.
The A8600 features three adjustable asynchronous peak cur-
rent mode buck regulators with internal MOSFETS. These three
regulators, SW1, SW2, and SW3, can continuously supply 1.0 A,
2.0 A and 2.5 A respectively. A synchronous controller, SW4, was
designed to deliver up to 4 A but can be configured for as much
as 8 A by setting the sense resistor accordingly.
SW1 is an always-on buck regulator that provides Low Quiescent
Input Current (Low IQ) mode. When the EN/SYNC and ACCI
pins are held low, SW1 employs pulse frequency modulation
(PFM) to draw only 10s of microamperes from the input supply
while delivering 3.3V, 5.0V, or 6.5V at no load.
SW4 is an adjustable, synchronous, peak current mode buck
controller with internal MOSFET gate drivers and externally
adjustable current limit.
In addition, the A8600 incorporates two 1 Ω high-side switches,
S1 and S2) which typically provide 250 mA (DC) and 450 mA
(peak), with foldback type overcurrent protection. For thermal
reasons, S1 and S2 are allowed to be on only for input voltages
up to approximately 18.3 V.
The A8600 also offers two detectors (that is, comparators) for
sensing both battery voltage (BU circuit) and battery voltage
remotely applied through a key type ignition switch (ACC cir-
cuit). There is also a Mute output with a programmable delay set
by a capacitor at the CTMR pin.

Reference Voltage

The A8600 incorporates an internal reference that allows output
voltages as low as 0.8 V. The accuracy of the internal reference is
±1.5% across the operating temperature range. The output volt-
age of each regulator is adjusted by connecting a resistor divider
between the respective V
SWx
as shown in the Typical Application diagram.

PWM Switching Frequency

The PWM switching frequency of the A8600 is fixed at 425 kHz
and has an accuracy of ±15% across the operating temperature
Quadruple Output Regulator with Two High-Side Switches,

Functional Description

nodes and FBx pins of the A8600,
BU/ACC Voltage Detectors, and Mute Delay
range. The four buck switchers are interleaved at 180° intervals:
SW1 and SW3 turn on at 0°, and SW2 and SW4 turn on at 180°.
During startup, the PWM switching frequency is reduced to 50%
of the nominal frequency until FBx exceeds 300 mV. This is
done to improve output regulation when V
upward and the PWM control loop is operating at the minimum
controllable on-time and requires very low duty cycles.
If the voltage at the FBx pin is less than 300 mV, and the COMPx
voltage reaches its maximum level, the PWM switching fre-
quency is reduced to 25% of the nominal frequency. This is done
because a very low FBx voltage combined with a maximum
COMPx voltage indicates the regulator output is shorted to
ground. The extra-low switching frequency allows additional off
(decay) time between LXx pulses so the inductor current does
not climb to a value that may damage the A8600 or the output
inductor.

Enable/Synchronization Input (EN/SYNC)

The Enable/Synchronization input (EN/SYNC pin) provides two
major functions. First, the EN/SYNC pin is a control input that
sets the operating mode of the A8600. When EN/SYNC is a logic
high, all 4 switchers operate in PWM mode and the high-side
switches turn on or off via the ENS input. When EN/SYNC is
a logic low, SW1 operates in low current keep-alive (Low IQ)
mode, and SW2, SW3, SW4, S1, and S2 are turned off.
Second, when an external clock is applied to the EN/SYNC pin,
the A8600 wakes-up, completes soft start at the nominal PWM
frequency, and then synchronizes its PWM to the external clock.
The external clock may be used to either increase or decrease the
A8600 nominal PWM frequency. Synchronization operates when
PWM is in the range from 325 to 550 kHz. When using synchro-
nization, the external clock pulses must satisfy the pulse width,
duty cycle, and rise/fall time requirements shown in the Electrical
Characteristics table in this data sheet.
When EN/SYNC transitions to logic high, the A8600 turns on
and then, provided there are no fault conditions, SW2, SW3, and
SW4 initiate soft start and the output voltages will ramp to their
final voltage in the time set by the soft start capacitors (CSSx).
When EN/SYNC transitions to low, then the A8600 will wait
2048 PWM cycles before transitioning SW1 from PWM to PFM
mode. However after EN/SYNC transitions to low, the A8600
will wait only 15 PWM cycles before shutting off SW2, SW3,
SW4, S1, and S2.
is starting to ramp
SWx
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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