Pcb Component Placement And Routing - Allegro MicroSystems A8600 Manual

Quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay
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A8600
where I
is the regulator output current, ΔI
SWx
peak inductor ripple current, R
the high-side MOSFET, and V
asynchronous diode.
The R
of the high-side MOSFET will have some initial
DS(on)
tolerance plus an increase from self-heating and elevated ambi-
ent temperatures. A conservative design should accommodate
an R
with at least a 15% initial tolerance plus 0.39%/°C
DS(on)
increase due to temperature.
The sum of the power dissipated by the internal gate driver can
be calculated using the following equation:
P
= (3 × Q
DRIVER
where V
is the gate drive voltage (typically 5 V for all
GS
four buck switchers), Q
is the gate charge to drive internal
G
MOSFET1/2/3 to V
= 5 V (about 2.5 nC each), Q
GS
charge to drive the external MOSFET to V
come from the MOSFET datasheet), and f
ing frequency.
The power dissipated by the high-side switches (S1, S2) can be
calculated using th following equation:
P
= I
S1/S2
where I
is the DC current through high-side switches S1 and S2,
x
and R
is the on-resistance of the switch (typically 1 Ω),
DS(on)Sx
Finally, the total power dissipated (P
vious equations for all four switchers and the high-side switches:
P
= P
TOTAL
INTOTAL
The average junction temperature can be calculated with the fol-
lowing equation:
T
= P
J
TOTAL
where P
is the total power dissipated as described in
TOTAL
equation 40, R
is the junction-to-ambient thermal resistance
θJA
(23°C/W on a 4-layer PCB), and T
Quadruple Output Regulator with Two High-Side Switches,
is the peak-to-
Lx
is the on-resistance of
DS(on)HSx
is the forward voltage of the
fx
+ Q
) × V
× f
G
G4
GS
SW
is the gate
G4
= 5 V (this must
GS
is the PWM switch-
SW
2
× R
S1/S2
DS(on)S1/S2
) is the sum of the pre-
TOTAL
+ P
+ P
+ P
SW1/2/3
DRIVER
S1/S2
+ R
+ T
θJA
A
is the ambient temperature.
A
BU/ACC Voltage Detectors, and Mute Delay
The maximum junction temperature will be dependent on how
efficiently heat can be transferred from the PCB to ambient air.
The thermal pad on the bottom of the IC should be connected
to a at least one ground plane using multiple vias for optimum
performance. A small amount of airflow can improve the thermal
performance considerably.
As with any regulator, there are limits to the amount of power
that can be delivered and heat that can be dissipated before
risking thermal shutdown. There are tradeoffs between ambient
operating temperature, input voltage, output voltage, output cur-
rent, switching frequency, PCB thermal resistance, airflow, and
other nearby heat sources. Even a small amount of airflow will
(38)
will reduce junction temperature considerably.

PCB Component Placement and Routing

A good PCB layout is critical if the A8600 is to provide clean,
stable output voltages. Follow these guidelines to insure good
PCB layout. Figure 28 shows a typical buck converter schematic
with the critical power paths/loops. Figure 29 shows an example
PCB component placement and routing (for SW3) with the same
critical power paths/loops from the schematic.
1) By far, the highest di/dt in the asynchronous buck regulator
(39)
occurs at the instant the upper FET turns on and the capacitance
of the asynchronous Schottky diode (200 to 1000 pF) is quickly
charged to V
. The ceramic input capacitors must deliver this
INx
fast, short pulse of current. Therefore, the loop from the ceramic
input capacitors through the upper FET and into the asynchro-
nous diode to ground should be minimized. Ideally these compo-
nents are all connected using only the top layer traces (that is, do
(40)
not use vias to other power or signal layers).
2) When the upper FET is on, current flows from the input supply
and capacitors, through the upper FET, into the load via the out-
(41)
put inductor, and back to ground. This loop should be minimized
and have relatively wide traces.
3) When the upper FET is off, free-wheeling current flows from
ground, through the asynchronous diode, into the load via the
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
45

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