Advanced Chipset Features - Shuttle AB49 User Manual

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Advanced Chipset Features

These items define critical timing parameters of the mainboard. You should
leave the items on this page at their default values unless you are very
familiar with the technical, specifications of your system hardware. If you
change the values incorrectly, you may introduce fatal errors or recurring
instability into your system.
DRAM Timing Selectable
The value in this field depends on performance parameters of the
installed memory chips(DRAM). Don't change the value from the
factory setting unless you install new memory that has a different perfor-
mance rating than the original DRAMs.
Ø The Choice: Manual or By SPD.
CAS Latency Time
This item defines the timing delay in clock cycles before SDRAM starts a
read command after receiving it.
Ø The Choice: 1.5, 2, 2.5, or 3.
Active to Precharge Delay
This item defines the numbers of cycles for RAS to be allowed to precharge.
Ø The Choice: 7, 6, or 5.
DRAM RAS# to CAS# Delay
This item defines the timing of the transition from RAS (row address strobe)
to CAS (column address strobe) as both rows and columns are separately
addressed shortly after DRAM is refreshed.
Ø The Choice: 3 or 2.
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