Advanced Chipset Features - Shuttle ME21 User Manual

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Advanced Chipset Features

This section allows you to configure the system based on the specific
features of the installed chipset. This chipset manages bus speeds and
access to system memory resources, such as DRAM and the external
cache. It also coordinates communications between the conventional
ISA bus and the PCI bus. It states that these items should never need to
be altered.
The default settings have been chosen because they provide the best
operating conditions for your system. If you discovered that data was
being lost while using your system, you might consider making any
changes.
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing.
" The Choice: 2 or 3
SDRAM Cycle Time Tras/Trc
Selects the number of SCLKs for an access cycle.
" The Choice: 5/7, 7/9, or Auto.
SDRAM RAS-to-CAS Delay
This field lets you insert a timing delay between the CAS and RAS
strobe signals, and you can use it when DRAM is written to, read from,
or refreshed. Faster performance is gained in high speed, more stable
performance, in low speed. This field is applied only when synchro-
nous DRAM is installed in the system.
" The Choice: 3, 2, or Auto.
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