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Auto Configuration
DRAM Speed Selection
MA Wait State
EDO RAS # TO CAS# Delay
EDO RAS # Time
EDO DRAM Read Burst
EDO DRAM Write Burst
DRAM ECC Select
CPU- TO -PCI IDE Posting
System BIOS Cacheable
Video BIOS Cacheable
Video RAM Cacheable
8 bit I/ O Recovery Time
16 bit I/ O Recovery Time
Memory Hole At 15M-16M
Passive Release
Delayed Transaction
AGP Aperture Size (MB)
SDRAM RAS- to - CAS Delay
Time
SDRAM RAS
The following indicates the options of each item and describes their meaning.
Item
• Auto Configuration
• DRAM Speed
Selection
• MA Wait State
• EDO RAS# To
CAS# Delay
• EDO RAS#
Time
• EDO DRAM Read
Burst
ROM PCI/ISA BIOS (2A69JQ1K)
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
: Enabled
: 60ns
: Slow
: 3
: 3
: X333
: X222
: Disabled
: Enabled
: Disabled
: Disabled
: Disabled
: 1
: 1
: Disabled
: Enabled
: Enabled
: 64
: Slow
: Slow
Figure-5 Chipset Features Setup Menu
Option
Enabled
Automatically configures DRAM Timing according
to the value of "DRAM Speed Selection".
Manually configure.
Disabled
Note: It is recommended that
option be chosen by common users.
50ns,
This item is of selected EDO DRAM read/write timing. You
must ensure that your DIMMs are as fast as 50ns, otherwise
60ns
60ns should be selected.
Slow
One additional wait state is inserted before the
assertion of the first MA and CAS#/RAS# during
DRAM read or write leadoff cycles. This affects
page hit, row miss and page miss cases.
Without additional wait state.
Fast
2
Adds a delay time between the assertion of RAS#
and CAS#
3
Without additional delay time.
3
DRAM RAS# time=3x system clocks.
DRAM RAS# time=4x system clocks.
4
× 3 3 3,
The DRAM read burst timing depends on the type
× 2 2 2,
of DRAM on a per-row basis. Slower rates may be
required to support slower DRAM.
SDRAM CAS latency Time : 3
ESC: Quit ↑↓→←: Select Item
F1: Help
PU/PD/+/- : Modify
F5: Old Values (Shift)F2: Color
F7: Load Setup Defaults
Description
the "Enabled"
3 -
Chapter 3
7
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