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Pin
Side B
Signal
14
Reserved
15
Ground
16
CLK
17
Ground
18
REQ#
19
+5V
20
AD[31]
21
AD[29]
22
Ground
23
AD[27]
24
AD[25]
25
+3.3V
26
C/BE[3]#
27
AD[23]
28
Ground
29
AD[21]
30
AD[19]
31
+3.3V
32
AD[17]
33
C/BE[2]#
34
Ground
35
IRDY#
36
+3.3V
37
DEVSEL#
38
Ground
39
LOCK#
40
PERR#
41
+3.3V
42
SERR#
43
+3.3V
44
C/BE[1]#
45
AD[14]
46
Ground
47
AD[12]
48
AD[10]
49
Ground
50
Key
51
52
AD[08]
53
AD[07]
54
+3.3V
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Description
Clock
Request
+5 V power
Address / Data 31
Address / Data 29
Address / Data 27
Address / Data 25
+3.3 V power
Command, Byte Enable 3
Address / Data 23
Address / Data 21
Address / Data 19
+3.3 V power
Address / Data 17
Command, Byte Enable 2
Initiator Ready
+3.3 V power
Device Select
Lock bus
Parity Error
+3.3 V power
System Error
+3.3 V power
Command, Byte Enable 1
Address / Data 14
Address / Data 12
Address / Data 10
Address / Data 08
Address / Data 07
+3.3 V power
ATX-HSW-S - User Guide, Rev. 1.1
Side A
Signal
Description
+3.3VAUX
+3.3 V auxiliary power
RST#
Reset
+5V
+5 V power
GNT#
Grant PCI use
Ground
PME#
Power Management Event
AD[30]
Address / Data 30
+3.3V
+3.3 V power
AD[28]
Address / Data 28
AD[26]
Address / Data 26
Ground
AD[24]
Address / Data 24
IDSEL0
Initialization Device Select
+3.3V
+3.3 V power
AD[22]
Address / Data 22
AD[20]
Address / Data 20
Ground
AD[18]
Address / Data 18
AD[16]
Address / Data 16
+3.3V
+3.3 V power
FRAME#
Address or Data phase
Ground
TRDY#
Target Ready
Ground
STOP#
Stop Transfer Cycle
+3.3V
+3.3 V power
SMB_CLK
System Management Bus Clock
SMB_DAT
System Management Bus Data
Ground
PAR
Parity
AD[15]
Address / Data 15
+3.3V
+3.3 V power
AD[13]
Address / Data 13
AD[11]
Address / Data 11
Ground
AD[09]
Address / Data 09
C/BE[0]#
Command, Byte Enable 0
+3.3V
+3.3 V power
AD[06]
Address / Data 06
// 56
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