Xilinx Virtex-6 FPGA Getting Started Manual page 11

X-Ref Target - Figure 1
Software Hardware
Figure 1: Block Diagram of the Virtex-6 FPGA Targeted Reference Design
The Virtex-6 FPGA Connectivity TRD features these components:
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Virtex-6 FPGA Connectivity Kit Getting Started
UG664 (v1.4) July 6, 2011
Getting Started with the Connectivity Targeted Reference Design Demo
@250 MHz
64
S2C_Data
S2C_Ctrl
C2S_Ctrl
C2S_Data
64
Packet
DMA
64
S2C_Data
S2C_Ctrl
C2S_Ctrl
C2S_Data
64
@250 MHz
Register
Interface
Performance
Monitor
Integrated Blocks Xilinx IP
Virtex-6 FPGA Integrated Block for PCI Express core configured as a
4-lane at 5 Gb/s or 8-lane at 2.5 Gb/s Endpoint for PCI Express, v2.0
A performance monitor tracks the PCIe® data bandwidth by measuring data bus
utilization on:
• AXI4-Stream interface
Packet DMA for PCI Express from Northwest Logic, a multichannel DMA that:
• Supports full-duplex operation with independent transmit and receive paths
• Provides a packetized interface on the backend similar to LocalLink
• Monitors data transfers in the receive and transmit directions
• Provides a control plane interface to access user-defined registers
Multiport Virtual FIFO
• The Memory Interface Controller is delivered through the Virtex-6 FPGA Memory
Interface Generator (MIG) tool.
• The virtual FIFO is a highly efficient layer around the native interface of the
Virtex-6 FPGA Memory Controller and an external DDR3 memory device.
XAUI LogiCORE IP that utilizes serial I/O transceivers to provide a throughput of up
to 10 Gb/s
XAUI TX and XAUI RX blocks align data as per the XGMII format.
Control logic to interface between the DMA and the multiport Virtual FIFO.
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@250 MHz @156.25 MHz
64
Packet
WR_Data
Control
with CRC
Control
Control
Packet
Control
RD_Data
with CRC
64
Multiport
Virtual
FIFO
64
WR_Data
Control
Control
Control
Control
RD_Data
64
@250 MHz
User Space
Registers
@200 MHz
Third Party IP FPGA Logic
@156.25 MHz
64 64
XGMII
RD_Data Data
TX
Control Control
Control Control
XGMII
WR_Data Data
RX
64 64
64
RD_Data
Checker
Control
Control
Generator
WR_Data
64
@250 MHz
Native
256
Interface
@400 MHz
of DDR3
64
Memory
Controller
256
UG664_01_092810
DDR3
11