Evaluating The Virtex-6 Fpga Connectivity Trd - Xilinx Virtex-6 FPGA Getting Started Manual

Evaluating the Virtex-6 FPGA Connectivity TRD

The Virtex-6 FPGA Connectivity TRD provides a Performance and Status monitor
application and GUI. The application enables customers to evaluate different system
parameter optimizations. This section demonstrates key performance criteria for the
PCI Express, XAUI, and Raw Data Path (Memory) interfaces.
To evaluate the Virtex-6 FPGA Connectivity TRD:
1.
2.
Virtex-6 FPGA Connectivity Kit Getting Started
UG664 (v1.4) July 6, 2011
Launch the Performance Monitor for the Virtex-6 FPGA Connectivity TRD:
In Windows:
a. Double-click the xpmon icon on the desktop to launch the Performance Monitor
application.
In Linux:
a. Navigate to the v6_pcie_10Gdma_ddr3_xaui_axi folder.
b. Double-click v6_trd_lin_quickstart to launch the Performance Monitor and
Status GUI.
c. A window prompt appears as shown in
proceed.
Set up the test in the Performance Monitor:
a. Two Data Transmission options are provided:
- XAUI Path
- Raw Data Path
b. These Packet Size options are provided:
- XAUI Path
Minimum Packet Size: Choose a value between 64 - 16384 bytes
Maximum Packet Size: Choose a value between 64 - 16384 bytes
- Raw Data Path
Packet Size: Choose a value between 64 - 32768 bytes
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Evaluating the Virtex-6 FPGA Connectivity TRD
Figure 21. Click Run in Terminal to
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