Agilent Technologies Infiniium 80000 Series Service Manual page 153

Chapter 8: Theory of Operation
Block-Level Theory
Figure 8-2
Upper
Lower
Scope Front Panel
Acquisition Block Diagram
152
20 GSa ADC
8 Bit
Deceleration &
CLK
LSI Logic ASIC
8 Bit
CLK
Reference Clock
Generation
Interpolator
Sys
Trig
DACS
High Speed Trigger Circuitry
Trig 1
Clock Data
Delay Delay
Circuit Circuit
Calibrat
or,
Probe
Comp
& Trig
Out
Addr
PHI1
32 Bit
PHI2
Acquisition
Data
32 Bit
Memory
PHI3
Processing
64 Mbit RAM
32 Bit
PHI4
32 Bit
Clock
Data
Hold Off
ATrig
CH 4
CH 3
CH 2
CH 1
Comp.
Scope Back Panel
Secondary PCI Bus
PCI
FPGA
Bridge
Primary PCI Bus
Ribbon
Cable
INTERFACE
CARD
54856b01