Figure 5. Stm32F401Vct6 Block Diagram - ST STM32F401 User Manual

Hardware layout
NJTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
TRACECLK
TRACED[3:0]
PA[15:0]
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
PH[1:0]
up to 81 AF
D[7:0]
CMD, CK as AF
4 compl. channels TIM1_CH1[1:4]N,
4 channels TIM1_CH1[1:4]ETR,
BKIN as AF
2 channels as AF
1 channel as AF
1 channel as AF
RX, TX, CK,
CTS, RTS as AF
RX, TX, CK as AF
MOSI, MISO,
SCK, NSS as AF
MOSI, MISO,
SCK, NSS as AF
VDDREF_ADC
16 analog inputs
14/39

Figure 5. STM32F401VCT6 block diagram

JTAG & SW
MPU
ETM
NVIC
D-BUS
ARM Cortex-M4
84 MHz
I-BUS
FPU
S-BUS
8 Streams
DMA2
FIFO
8 Streams
DMA1
FIFO
GPIO PORT A
GPIO PORT B
GPIO PORT C
GPIO PORT D
GPIO PORT E
GPIO PORT H
EXT IT. WKUP
SDIO / MMC
TIM1 / PWM 16b
16b
TIM9
TIM10
16b
16b
TIM11
smcard
USART1
irDA
smcard
USART6
irDA
SPI1
SPI4
USART 2MBps Temperature sensor
ADC1 IF
@VDDA
DocID025174 Rev 1
Flash
up to
256 KB
SRAM 64 KB
AHB2 84 MHz
AHB1 84 MHz
@VDDA
RC HS
RC LS
PLL1&2
Reset &
clock
MANAGT
control
CRC
DMA2 DMA1
AHB/APB2 AHB/APB1
WWDG
DP
USB
DM
OTG FS
ID, VBUS, SOF
Power managmt
VDD
Voltage
VDD = 1.7 to 3.6 V
regulator
3.3 to 1.2 V
@VDD
VSS
POR
VCAP
Supply
reset
supervision
Int POR/PDR
VDDA, VSSA
BOR
NRST
PVD
@VDD
@VDDA
OSC_IN
XTAL OSC
OSC_OUT
4- 16MHz
WDG 32K
PWR
VBAT = 1.65 to 3.6 V
interface
@V BAT
OSC32_IN
XTAL 32 kHz OSC32_OUT
RTC
ALARM_OUT
AWU
Backup register
STAMP1
TIM2
4 channels, ETR as AF
32b
16b
TIM3 4 channels, ETR as AF
TIM4
16b 4 channels, ETR as AF
TIM5 32b 4 channels
smcard RX, TX as AF
USART2
irDA CTS, RTS as AF
MOSI/SD, MISO/SD_ext, SCK/CK
SP2/I2S2
NSS/WS, MCK as AF
MOSI/SD, MISO/SD_ext, SCK/CK
SP3/I2S3
NSS/WS, MCK as AF
I2C1/SMBUS SCL, SDA, SMBA as AF
I2C2/SMBUS SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
I2C3/SMBUS
UM1669
(PDR OFF)
1.8 to 3.6 V
(PDR ON)
MS31144V2