Xycom XVME-560 Manual page 56

XVME-560 Manual
September, 1984
Table B-1. Pl - VMEbus Signal Identification (cont'd)
Connector
Signal
and
Mnemonic
Pin Number
SYSCLK 1A: 10
SYSFAIL* 1C: 10
lC: 12
SYSRESET*
WRITE* 1A: 14
+5V STDBY 1B: 3
+5V
1A: 32
1B: 32
lC: 32
2B: 1,13,32
+ 1 2 v 1C: 31
-12v 1A: 31
Signal Name and Description
SYSTEM CLOCK - A constant 16-MHz clock signal
that is independent of processor speed or timing.
This signal is used for general system timing use.
SYSTEM FAIL - Open-collector driven signal that
indicates that a failure has occurred in the system.
This signal may be generated by any module on the
VMEbus.
SYSTEM RESET - Open-collector driven signal
which, when low, will cause the system to be reset.
WRITE - Three-state driven signal that specifies
the data transfer cycle in progress to be either
read or
written.
operation; a low level indicates a write operation.
+5 Vdc STANDBY - This line supplies +5 Vdc to
devices requiring battery
- Used by system logic circuits.
+5 Vdc Power
+12 Vdc Power -
Used by
-12 Vdc Power - Used by system logic circuits.
B-4
high indicates a read
A level
backup.
system logic circuits.