Xycom XVME-560 Manual page 51

XVME-560 Manual
1984
September,
INTERRUPT CONTROL
Interrupts for non-intelligent modules can be enabled or disabled by setting/clearing
the Interrupt Enable bit in the module status register. The status of pending on-board
interrupts can also be read from this register.
modules is handled by the Interprocessor Communications Protocol.
Communications Between Processors
Communications between an intelligent "master" and an intelligent "slave" I/O module
is governed by XYCOM's
involves the use of 20-byte Command Block data structures, which can be located
anywhere in shared global RAM or dual-access RAM on an I/O module, to exchange
commands and data between a host processor and an I/O module.
Communication Protocol is thoroughly explained in Chapter 3 of this manual.
THE KERNEL
To standardize its XVME I/O modules, XYCOM has designed them around " k e r n e l s "
common from module to module. Each different module type consists of a standard
kernel, combined with module-dependent application circuitry. Module standardiza-
tion results in more efficient module design and allows the implementation of the
Standard I/O Architecture.
modules is that it allows the use of a common command language or protocol
(Interprocessor Communication ProtocoI in this case).
The intelligent kernel is based around a 68000 microprocessor. This design provides
the full complement of VMEbus Requester and Interrupter options for master/slave
well
as
interfacing,
XYCOM Standard I/O Architecture (as covered earlier in this appendix).
The non-intelligent kernel provides the circuitry required to receive and generate all
of the signals for a
also employs the features of the XYCOM Standard I/O Architecture (as described
earlier in this appendix).
The simplified diagrams below show the features of both the intelligent and the non-
intelligent kernels.
Interprocessor Communication (IPC)
The biggest benefit of standardization for intelligent
all of the advantages provided by the various facets of the
as
VMEbus defined
Interrupt control for intelligent
16-bit "slave" module. The non-intelligent kernel
A - 9
Protocol. This protocol
Interprocessor