Renesas V850ES/GB1TM Manuals

Manuals and User Guides for Renesas V850ES/GB1TM. We have 1 Renesas V850ES/GB1TM manual available for free PDF download: User Manual

Renesas V850ES/GB1TM User Manual (498 pages)

Brand: Renesas | Category: Microcontrollers | Size: 2 MB

Preface
7
Table of Contents
9
Chapter 1 Introduction

23
- General
  
  23
- Device Features
  
  24
  - Table 1-1: Product Versions
    24
- Application Fields
  
  25
- Pin Configuration (Top View)
  
  26
  - Figure 1-1: Pin Configuration of the Μpd70F322X, Μpd70322X
    26
- Internal Architecture
  
  28
Chapter 2 Pin Functions

31
- List of Pin Functions
  
  31
  - Table 2-1: Pin List
    31
  - Table 2-2: Pin State Related to V850ES/GB1 State
    34
- Description of Pin Functions
  
  35
  - Figure 2-1: Pin I/O Circuits
    48
Chapter 3 CPU Functions

49
Chapter 4 Interrupt/Exception Processing Function

95
- Outline
  
  95
  - Features
    95
  - Table 4-1: Interrupt Source List
    96
- Non-Maskable Interrupt
  
  98
  - Operation
    99
  - Figure 4-1: Non-Maskable Interrupt Servicing
    99
  - Figure 4-2: Acknowledging Non-Maskable Interrupt Request
    100
  - Restore
    101
  - Figure 4-3: RETI Instruction Processing
    101
  - NP Flag
    102
  - Noise Elimination Circuit of NMI Pin
    102
  - Figure 4-4: NP Flag (NP)
    102
  - Edge Detection Function of NMI Pin
    103
  - Figure 4-5: NMI Edge Specification: INTM2 Register Format
    103
- Maskable Interrupts
  
  104
- Software Exception
  
  118
  - Operation
    118
  - Figure 4-19: Software Exception Processing
    118
  - Restore
    119
  - Figure 4-20: RETI Instruction Processing
    119
  - EP Flag
    120
  - Figure 4-21: EP Flag (EP)
    120
- Exception Trap
  
  121
  - Illegal Op Code Definition
    121
  - Figure 4-22: Illegal Op Code
    121
  - Operation
    122
  - Figure 4-23: Exception Trap Processing
    122
  - Restore
    123
  - Figure 4-24: RETI Instruction Processing
    123
- Priority Control
  
  124
- Interrupt Response Time
  
  127
  - Figure 4-25: Pipeline Operation During Interrupt Request Acknowledgment (Outline)
    127
- Periods in Which Interrupts Are Not Acknowledged by CPU
  
  128
- Key Interrupt Function
  
  129
Chapter 5 Clock Generator

131
Chapter 6 Timers

153
Chapter 7 Watch Timer

239
- Function
  
  239
  - Figure 7-1: Block Diagram of Watch Timer
    239
- Configuration
  
  240
- Watch Timer Control Register
  
  240
  - Figure 7-2: Watch Timer Mode Control Register (WTM) (1/2)
    240
  - Table 7-1: Configuration of Watch Timer
    240
- Operations
  
  242
Chapter 8 Watchdog Timer

245
- Features
  
  245
  - Figure 8-1: Block Diagram of Watchdog Timer
    246
- Configuration
  
  247
- Operation
  
  250
Chapter 9 Serial Interface Function

253
Chapter 10 DCAN

327
- Outline Description
  
  327
- CAN Protocol
  
  327
  - Figure 10-1: Structural Block Diagram
    327
  - Message Format
    328
  - Protocol Mode Function
    328
  - Data Frame / Remote Frame
    329
  - Figure 10-2: Data Frame
    329
  - Figure 10-3: Remote Frame
    329
  - Figure 10-4: Data Frame
    330
  - Figure 10-5: Arbitration Field/Standard Format Mode
    330
  - Figure 10-6: Arbitration Field/Extended Format Mode
    331
  - Table 10-1: Bit Number of the Identifier
    331
  - Table 10-2: RTR Setting
    331
  - Table 10-3: Mode Setting
    331
  - Figure 10-7: Control Field (Standard Format Mode)
    332
  - Figure 10-8: Control Field (Extended Format Mode)
    332
  - Table 10-4: Data Length Code Setting
    332
  - Figure 10-10: CRC Field
    333
  - Figure 10-9: Data Field
    333
  - Figure 10-11: ACK Field
    334
  - Figure 10-12: End of Frame
    334
  - Figure 10-13: Interframe Space/Error Active
    335
  - Figure 10-14: Interframe Space/Error Passive
    335
  - Table 10-5: Operation in the Error State
    335
  - Error Frame
    336
  - Figure 10-15: Error Frame
    336
  - Table 10-6: Definition of each Field
    336
  - Figure 10-16: Overload Frame
    337
  - Overload Frame
    337
  - Table 10-7: Definition of each Frame
    337
- Function
  
  338
  - Arbitration
    338
  - Bit Stuffing
    338
  - Table 10-8: Arbitration
    338
  - Table 10-9: Bit Stuffing
    338
  - Multi Master
    339
  - Multi Cast
    339
  - Sleep Mode/Stop Function
    339
  - Error Control Function
    340
  - Table 10-10: Error Types
    340
  - Table 10-11: Output Timing of the Error Frame
    340
  - Table 10-12: Types of Error
    341
  - Table 10-13: Error Counter
    342
  - Baud Rate Control Function
    343
  - Figure 10-17: Nominal Bit Time (8 to 25 Time Quanta)
    343
  - Table 10-14: Segment Name and Segment Length
    343
  - Figure 10-18: Adjusting Synchronization of the Data Bit
    344
  - Figure 10-19: Bit Synchronization
    345
  - State Shift Chart
    346
  - Figure 10-20: Transmission State Shift Chart
    346
  - Figure 10-21: Reception State Shift Chart
    347
  - Figure 10-22: Error State Shift Chart
    348
- Connection with Target System
  
  349
  - Figure 10-23: Connection to the CAN Bus
    349
- DCAN Controller Configuration
  
  350
- Special Function Register for DCAN-Module
  
  351
  - Table 10-15: Table of DCAN0 Sfr's
    351
  - Table 10-16: SFR Bit Names
    351
- Message Buffer Configuration
  
  352
- Transmit Buffer Structure
  
  353
- Transmit Message Buffer Format
  
  354
- Receive Buffer Structure
  
  358
- Receive Message Buffer Format
  
  359
- Mask Function
  
  366
- Operation of the DCAN Controller
  
  370
- Baud Rate Generation
  
  382
- Function Control
  
  389
  - Transmit Control
    389
  - Figure 10-47: Transmit Control Register (TCR0) (1/2)
    389
  - Receive Control
    391
  - Figure 10-48: Receive Message Register (RMES0)
    391
  - Mask Control
    392
  - Figure 10-49: Mask Control Register (MASKC0) (1/2)
    392
  - Table 10-19: Mask Operation Buffers
    393
  - Performance of the DCAN
    395
- Interrupt Information
  
  396
  - Interrupt Vectors
    396
  - Transmit Interrupt 0
    396
  - Receive Interrupt
    396
  - Table 10-20: Interrupt Sources
    396
  - Error Interrupt
    397
- Power Saving Modes
  
  398
  - CPU Halt Mode
    398
  - CPU WATCH Mode
    398
  - CPU Stop Mode
    398
  - DCAN Sleep Mode
    398
  - DCAN Stop Mode
    400
- Functional Description by Flowcharts
  
  401
  - Initialization
    401
  - Figure 10-50: Initialization Flow Chart
    401
  - Transmit Preparation
    402
  - Figure 10-51: Transmit Preparation
    402
  - Abort Transmit
    403
  - Figure 10-52: Transmit Abort
    403
  - Handling by the DCAN
    404
  - Figure 10-53: Handling of Semaphore Bits by DCAN-Module
    404
  - Receive Event Oriented
    405
  - Figure 10-54: Receive with Interrupt, Software Flow
    405
  - Receive Task Oriented
    406
  - Figure 10-55: Receive, Software Polling
    406
  - Figure 10-56: Receive, Software Polling in Case of Data New Flag Limitation
    407
  - Cautions
    408
Chapter 11 A/D Converter

409
Chapter 12 Port Functions

427
- Features
  
  427
- Port Configuration
  
  427
- Pin Functions of each Port
  
  437
  - Port 0
    437
  - Figure 12-7: Port 0 (P0)
    437
  - Figure 12-8: Port 0 Mode Control Register (PMC0)
    438
  - Figure 12-9: Port 0 Mode Register (PM0)
    439
  - Figure 12-10: Port 0 Pull-Up Resistor Option Register (PU0)
    439
  - Port 1
    440
  - Figure 12-11: Port 1 (P1)
    440
  - Figure 12-12: Port 1 Mode Control Register (PMC1)
    441
  - Figure 12-13: Port 1 Mode Register (PM1)
    442
  - Figure 12-14: Port 1 Pull-Up Resistor Option Register (PU1)
    442
  - Port 2
    443
  - Figure 12-15: Port 2 (P2)
    443
  - Figure 12-16: Port 2 Mode Control Register (PMC2)
    444
  - Figure 12-17: Port 2 Mode Register (PM2)
    445
  - Figure 12-18: Port 2 Pull-Up Resistor Option Register (PU2)
    445
  - Port 3
    446
  - Figure 12-19: Port 3 (P3)
    446
  - Figure 12-20: Port 3 Mode Control Register (PMC3)
    447
  - Figure 12-21: Port 3 Mode Register (PM3)
    448
  - Figure 12-22: Port 3 Pull-Up Resistor Option Register (PU3)
    448
  - Port 4
    449
  - Figure 12-23: Port 4 (P4)
    449
  - Figure 12-24: Port 4 Mode Control Register (PMC4)
    450
  - Figure 12-25: Port 4 Mode Register (PM4)
    451
  - Figure 12-26: Port 4 Pull-Up Resistor Option Register (PU4)
    451
  - Port 5
    452
  - Figure 12-27: Port 5 (P5)
    452
  - Figure 12-28: Port 5 Mode Control Register (PMC5)
    452
  - Figure 12-29: Port 5 Mode Register (PM5)
    453
  - Figure 12-30: Port 5 Pull-Up Resistor Option Register (PU5)
    453
  - Port 7
    454
  - Figure 12-31: Port 7 (P7, P7L and P7H)
    454
  - Port NMI
    456
  - Figure 12-32: Port NMI (PNMI)
    456
  - Port DL
    457
  - Figure 12-33: Port DL (PDL, PDLL and PDLH)
    457
  - Figure 12-34: Port DL Mode Register (PMDL, PMDLL and PMDLH)
    458
  - Port DH
    459
  - Figure 12-35: Port DH (PDH)
    459
  - Figure 12-36: Port DH Mode Register (PMDH)
    459
  - Port CS
    460
  - Figure 12-37: Port CS (PCS)
    460
  - Figure 12-38: Port CS Mode Register (PMCS)
    460
  - Port CT
    461
  - Figure 12-39: Port CT (PCT)
    461
  - Figure 12-40: Port CT Mode Register (PMCT)
    461
  - Port CM
    462
  - Figure 12-41: Port CM (PCM)
    462
  - Figure 12-42: Port CM Mode Control Register (PMCCM)
    462
  - Figure 12-43: Port CM Mode Register (PMCM)
    463
Chapter 13 RESET Function

465
- Overview
  
  465
- Configuration
  
  465
  - Figure 13-1: Reset Block Diagram
    465
- Operation
  
  466
  - Table 13-1: Hardware Status on RESET Pin Input or Occurrence of WDTRES
    466
- RAM Usage after RESET Release
  
  467
Chapter 14 ROM Correction Function

469
Chapter 15 Flash Memory (Μpd70F322X Only)

475
- Features
  
  475
- Writing by Flash Writer
  
  476
- Programming Environment
  
  476
  - Figure 15-1: Programming Environment in Conjunction with External Flash Writer
    476
- Communication System
  
  477
  - Figure 15-2: Flash Writer Communication Via CSI0
    477
  - Figure 15-3: Flash Writer Communication Via UART
    478
- Flash Programming Circuitry
  
  479
  - Figure 15-4: Minimal Circuitry for Flash Programming
    479
- Pin Handling
  
  480
  - VPP Pin
    480
  - Figure 15-5: Pin Handling of V
    480
  - Serial Interface Pins
    481
  - Figure 15-6: Conflict between Flash Writer and Other Output Pin
    481
  - Table 15-1: Serial Interface Pins
    481
  - Figure 15-7: Malfunction of Other Input Pins
    482
  - RESET Pin
    483
  - NMI Pin
    483
  - Flash Memory Programming Mode
    483
  - Port Pins
    483
  - Other Signal Pins
    483
  - Power Supply
    483
  - Figure 15-8: Conflict between Flash Writer Reset Line and Reset Signal Generation Circuit
    483
- Programming Method
  
  484

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Renesas V850ES/GB1TM Manuals

Renesas V850ES/GB1TM User Manual (498 pages)

Table of Contents

Chapter 1 Introduction

General

Device Features

Application Fields

Pin Configuration (Top View)

Internal Architecture

Chapter 2 Pin Functions

List of Pin Functions

Description of Pin Functions

Chapter 3 CPU Functions

Features

CPU Register Set

Operation Modes

Address Space

Chapter 4 Interrupt/Exception Processing Function

Outline

Non-Maskable Interrupt

Maskable Interrupts

Software Exception

Exception Trap

Priority Control

Interrupt Response Time

Periods in Which Interrupts Are Not Acknowledged by CPU

Key Interrupt Function

Chapter 5 Clock Generator

Features

Main System Clock Oscillator

Subsystem Clock Oscillator

Control Registers

System Operating Modes

Chapter 6 Timers

16-Bit Timer G0 (TMG0)

16-Bit Timer C (TMC0)

Timer Input Select

8-Bit Timer 50, Timer 51, Timer 52

Chapter 7 Watch Timer

Function

Configuration

Watch Timer Control Register

Operations

Chapter 8 Watchdog Timer

Features

Configuration

Operation

Chapter 9 Serial Interface Function

Features

Serial Interface Uart6N

Clocked Serial Interfaces 0, 1 (CSI00, CSI01)

Chapter 10 DCAN

Outline Description

CAN Protocol

Function

Connection with Target System

DCAN Controller Configuration

Special Function Register for DCAN-Module

Message Buffer Configuration

Transmit Buffer Structure

Transmit Message Buffer Format

Receive Buffer Structure

Receive Message Buffer Format

Mask Function

Operation of the DCAN Controller

Baud Rate Generation

Function Control

Interrupt Information

Power Saving Modes

Functional Description by Flowcharts

Chapter 11 A/D Converter

A/D Converter Functions

A/D Converter Configuration

A/D Converter Control Registers

A/D Converter Operations

A/D Converter Precautions

Chapter 12 Port Functions

Features

Port Configuration

Pin Functions of each Port