Reliance electric S-D4024 Engineering Manual page 31

Channel 1
Serial
Channel 2
Serial
Channel 3
Serial
8 MHz
Oscillator
Latch controller, internal register for data preparation,
error status preparing circuit, and registers 0 to 7
exist within PLD (84 pins).
Block Diagram
Figure B.1 illustrates a block diagram showing circuit organization of the PSC5000
Serial Absolute Encoder Input Card II (S-ABS II Card) briefly.
Protection
Circuit
Protection
Circuit
Protection
Circuit
1st
Data
Gate
Array
2nd
Data
1st
Data
Gate
Array
2nd
Data
1st
Data
Gate
Array
2nd
Data
Preparing Circuit
Latch
Controller
Figure B.1 - Block Diagram of the S-ABS II Card
DC/DC
ISOL5V
Converter
Effective
Data
Effective
Data
Effective
Data
Error Status
Status Display
by LED
A
PPENDIX
Block Diagram
5V
PSC5000 Bus
Register 0
Register 2
Register 4
Register 6
Register 7
Arbitration
Address
Decoder
Total
15 LEDs
B
Data
(16 bits)
Address
(19 bits)
XACKL
BERRL
Bus Clock
12 MHz
B-1