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Diagrams; Block Diagram - Input Section - Sony TA-ZH1ES Service Manual

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TA-ZH1ES
SECTION 5

DIAGRAMS

5-1.

BLOCK DIAGRAM - INPUT Section -

J400
COAX IN
OPTICAL
OPT IN
RECEIVER
IC400
J5101
L
LINE IN
R
R-CH
J5102
CENTER VOLTAGE
AD5V
GENERATOR
IC5401 (2/2)
USB SWITCH
IC503
2
3
2D+
D+
8
CN4201
3
WALKMAN
4
2D–
D–
7
1
3
1
1D+
CN501
2
USB-B
1D–
2
1
9
S4201
WALKMAN
VOLTAGE
DETECT
DETECTOR
IC511
OVER VOLTAGE
PROTECTION
CONTROLLER
IC508
11
9
TA-ZH1ES
WAVE
SHAPER
58
IC401
63
LINE AMP
45
IC5401 (1/2)
R-CH
44
MULTIPLEXER
IC5404
12
0X
X-COM
13
14
1X
LOW-PASS
FILTER
IC5403
USB CONTROLLER
IC506
PCM-DATA DSD-L
M19
USB0_DP
DX0 E1
PCM-DATA DSD-R
M18
USB0_DM
AXR9/DX1 C3
PCM-LRCK
FSX0 E3
FSX1 C5
PCM-BCK, DSD-BCK
CLKX0 D3
CLKX1 B3
CLKS0 F3
CLKS1 E4
K19
OSCOUT
X500
26MHz
GP1[4] G18
L19
OSCIN
GP1[5] G16
USB
SERIAL FLASH
N19
USB0_VBUS
SELECTOR
IC505
IC504
SPI1_SIMO G17
5
SI/SIO0
SPI1_SOMI H17
2
SO/SIO1
SPI1_CLK G19
SCLK
6
SPI1_SCS[0] E19
1
CS
H3 V15 K3 R5 W14 K4 J3 K14
30 31 29 26 32 27 28 33
SYSTEM CONTROLLER
IC601 (1/5)
DIGITAL AUDIO INTERFACE RECEIVER,
A/D CONVERTER
IC402
RXIN6
DATAOUT 16
9 SDTI
BCKOUT 14
8
LRCKOUT 15
7
RXIN1
XOUT
31
X400
24.576MHz
XIN
32
ADINL
ADINR
39 38 37 36 40 41 35 23 24
FREQUENCY
DIVIDER
IC403
60 61 62 50 85 82 48 83 84
59
34
34
SAMPLE RATE
CONVERTER
IC405
SDTO
24
IBCK
OBICK
25
ILRCK
OLRCK
26
OMCLK 27
19 20 21 15 4 3
A/D CONVERTER
IC406
47 AIN1P
28
SDTO1
LRCK/DSDOL1 26
48
AIN1N
TDMIN/DSDOR1
27
BICK/DCLK
25
5
AIN2P
R-CH
MCLK 16
4
AIN2N
31 33 20
18 19 20 15 21 14
34 35 12
EEPROM SDA
EEPROM SCL
FPGA
IC700 (1/3)
H1 IO/DIFFIO_L13N
G1 CLK1/DIFFCLK_0N
E1 IO/DIFFIO_L8N
1/2 RVS_MCK_OUT
AA3 IO/PLL1_CLKOUTP
A17 IO/DIFFIO_T31N/PADD1
A15 IO/DIFFIO_T27N/PADD5
A14 IO/DIFFIO_T25N/PADD9
A16 IO/DIFFIO_T30N
A12 CLK8/DIFFCLK_5N
A9
IO/DIFFIO_T20N/PADD16
A10
IO/DIFFIO_T21N
A6
IO/DIFFIO_T15N/PADD19
A8
IO/DIFFIO_T17N/DATA2
A11
CLK10/DIFFCLK_5N
RVS_MCK_OUT
>001B
(Page 36)
R-ch is omitted due to same as L-ch.
SIGNAL PATH
: LINE IN
: OPT IN
: COAX IN
: AUDIO (DIGITAL)
: USB
EEPROM
IC602
51
5 SDA
52
6 SCL
X1
71
X600
4MHz
X0
70

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