Prescaler Operations - ZiLOG Z8 Series User Manual

The counter timers remain at rest as long as the Enable Count bits are 0. To enable count-
ing, the Enable Count bit (D
starts when the Enable Count bit is written by an instruction. The first decrement occurs
four internal clock periods after the Enable Count bit has been set. If T1 is configured to
use an external clock, the first decrement begins on the next clock period. The Load and
Enable Count bits can be set at the same time. For example, using the instruction:
OR TMR,#03h
sets both D0 and D1 of the TMR. This loads the initial values of PRE0 and T0 into their
respective counters and starts the count after the M2T2 machine state after the operand is
fetched (see
M3
T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3

Prescaler Operations

During counting, the programmed clock source drives the 6-bit Prescaler Counter. The
counter is counted down from the value specified by bits of the corresponding Prescaler
Register, PRE0 (bit 7 to bit 2) or PRE1 (bit 7 to bit 2; see
UM001604-0108
for T0 and D
1
Figure 74).
R243 PRE1
Prescaler 1 Register
(% F3; Write-Only)
R245 PRE0
Prescaler 0 Register
(% F5; Write-Only)
Figure 74. Starting The Count
M1 M2
Figure 75. Counting Modes
for T1) must be set to 1. Counting actually
3
D0
Count Mode
0 = T Single Pass
1
1 = T Modulo-n
1
Mn
First Decrement Occurs
Four Clock Periods Later
TMR is Written, Counter/Timer
is Loaded
#03h is Fetched
Figure 70
®
Z8 CPU
User Manual
and Figure 71 on page
Counters and Timers
84