ZiLOG Z8 Series User Manual page 252

Test Under Mask
Syntax
TM dst, src
Instruction Format
OPC
OPC
OPC
Operation
dst AND src
This instruction tests selected bits in the destination operand for a 0 logical value. The bits
to be tested are specified by setting a 1 bit in the corresponding bit position in the source
operand (the mask). The TM instruction ANDs the destination operand with the source
operand (the mask). The Zero (Z) Flag can then be checked to determine the result. If the
Z Flag is set, then the tested bits were 0. When the TM operation is complete, the destina-
tion and source operands still contain their original values.
Flag
Z
S
V
D
H
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the
source or destination Working Register operand is specified by adding
high nibble of the operand. For example, if Working Register
operand, then
E
UM001604-0108
dst src
src dst
dst src
Description
Set if the result is zero; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Always reset to 0.
Unaffected
Unaffected
is used as the destination operand in the Op Code.
ECh
src or E
Address Mode
OPC
Cycles (Hex) dst
6 72
6 73
10 74
10 75
10 76
10 77 IR
dst
®
Z8
User Manual
src
r r
r lr
R R
R IR
R IM
IM
( ) to the
1110b Eh
is the destination
R12 (CH)
Instruction Description
CPU
245