Counter/Timer Operation; Load And Enable Count Bits - ZiLOG Z8 Series User Manual

Counter/Timer Operation

Under software control, counter/timers are started and stopped via the Timer Mode Regis-
ter (TMR,
bit and an Enable Count bit.

Load and Enable Count Bits

Setting the Load bit (D0 for T0 and D2 for T1) transfers the initial value in the prescaler
and the counter/timer registers into their respective down-counters. The next internal
clock resets bits D0 and D2 to 0, readying the Load bit for the next load operation. New
values may be loaded into the down-counters at any time. If the counter/timer is running, it
continues to do so and starts the count over with the new value. Therefore, the Load bit
actually functions as a software re-trigger.
UM001604-0108
R242 T1
Counter/Timer 1 Register
(%F2; Write/Read Only)
R244 T0
Counter/Timer 0 Register
(%F4; Write/Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Initial value when written
(Range 1-256 decimal, 01-00 HEX)
current value when read
Figure 72. Counter/Timer 0 and 1 Registers
) bits D0–D3 (see Figure
F1h
R241 TMR
Timer Mode Register
(% F1; Read/Write)
D3 D2 D1 D0
Figure 73. Timer Mode Register
73). Each counter/timer is associated with a Load
0 = No Function
1 = Load T
0
0 = Disable T Count
0
1 = Enable T Count
0
0 = No Function
1 = Load T
1
0 = Disable T Count
1
1 = Enable T Count
1
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Z8 CPU
User Manual
Counters and Timers
83