ZiLOG Z8 Series User Manual page 230

Rotate Right
Syntax
RR dst
Instruction Format
OPC
Operation
C ← dst(0)
dst(0) ← dst(1)
dst(1) ← dst(2)
dst(2) ← dst(3)
dst(3) ← dst(4)
dst(4) ← dst(5)
dst(5) ← dst(6)
dst(6) ← dst(7)
dst(7) ← dst(0)
The contents of the destination operand are rotated to the right by one bit position. The ini-
tial value of bit 0 is moved to bit 7 and also into the C Flag, as shown below.
D7 D6 D5 D4 D3 D2 D1 D0
Flag Description
C Set if the bit rotated from the least significant bit position was 1 (that is, bit 0 was 1).
Z Set if the result is zero; cleared otherwise.
S Set if the result bit 7 is set; cleared otherwise.
V Set if arithmetic overflow occurred (if the sign of the destination operand changed
during rotation); cleared otherwise.
D Unaffected
H Unaffected
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the
destination Working Register operand is specified by adding
of the operand. For example, if Working Register R12 (CH) is the destination operand, then
is used as the destination operand in the Op Code.
ECh
UM001604-0108
OPC
Cycles (Hex)
6
dst
6
Address Mode
dst
E0 R
E1 IR
C
1110b
®
Z8 CPU
User Manual
( ) to the high nibble
Eh
Instruction Description
223