Extended Bus Timing - ZiLOG Z8 Series User Manual

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Z8 CPU
User Manual
137

Extended Bus Timing

Some products can accommodate slow memory access time by automatically inserting an
additional software controlled state time (Tx). This stretches the DS timing by two clock
periods. Figure 128 and Figure 129 on page 138 display extended external memory Read
and Write cycles.
Machine Cycle
T1
T3
T2* TX
Clock
A15-A8 A15-A8
AD7–AD0 A7–A0
D7–D0 IN
AS
DS
R/W
DM
Read Cycle
*
Port inputs are strobed during T2, which is two internal system clocks
before the execution of the current instruction.
Figure 128. Extended External Instruction Fetch or Memory Read Cycle
UM001604-0108 External Interface