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Summary of Contents for GOWIN DK START GW1NSR-LV4CQN48PC7I6 V
- Page 1 DK_START_GW1NSR-LV4CQN48PC7I6_V User Guide DBUG388-1.0E, 01/21/2021...
- Page 2 Copyright©2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. No part of this document may be reproduced or transmitted in any form or by any denotes, electronic, mechanical, photocopying, recording or otherwise, without the prior written consent of GOWINSEMI. Disclaimer ®...
- Page 3 Revision History Date Version Description 01/21/2021 1.0E Initial version published.
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Page 4: Table Of Contents
Contents Contents Contents ....................... i List of Figures ....................iii List of Tables ...................... iv 1 About This Guide ..................1 1.1 Purpose ..........................1 1.2 Supported Products ......................1 1.1 Related Documents ......................1 1.2 Terminology and Abbreviations ................... 2 1.3 Support and Feedback ....................... - Page 5 3.9.1 Overview ........................17 3.9.2 MIPI/LVDS Circuit ......................17 3.9.3 Pins Distribution ......................18 3.10 RS232 ..........................20 3.10.1 Overview ........................20 3.10.2 RS232 Circuit ....................... 20 3.10.3 Pins Distribution ......................20 4 Precautions ....................21 5 Gowin Software ................... 22 DBUG388-1.0E...
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Page 6: List Of Figures
List of Figures List of Figures Figure 2-1 DK_START_GW1NSR-LV4CQN48PC7I6_V1.1 .............. 3 Figure 2-2 A Development Board Suite ..................... 4 Figure 2-3 PCB Components ......................5 Figure 2-4 System Block Diagram ..................... 6 Figure 3-1 Connection Diagram for FPGA USB ................10 Figure 3-2 FPGA J-LINK Connection Diagram .................. - Page 7 List of Tables List of Tables Table 1-1 Terminology and Abbreviations ..................2 Table 2-1 Development Board Specification ..................7 Table 3-1 FPGA Download Pins Distribution ..................11 Table 3-2 FPGA Power Pins Distribution ................... 12 Table 3-3 FPGA Clock and Reset Pins Distribution ................13 Table 3-4 LED Pins Distribution ......................
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Page 8: About This Guide
UG864, GW1NSR-4 Pinout UG865, GW1NSR-4C Pinout DS881, GW1NSER series FPGA Products Data Sheet UG884, GW1NSER series of FPGA Products Package and Pinout Manual UG883, GW1NSER-4C Pinout UG290, Gowin FPGA Products Programming and Configuration Guide SUG100, Gowin Software User Guide DBUG388-1.0E 1(22) -
Page 9: Terminology And Abbreviations
Serial Peripheral Interface Phase-locked Loop QN48 QFN48 1.3 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways. Website: www.gowinsemi.com E-mail: support@gowinsemi.com... -
Page 10: Development Board Introduction
2 Development Board Introduction 2.1 Overview Development Board Introduction Take GW1NS-4C for an instance, this chapter mainly introduces the composition, functions and features of the development board. Compared to the GW1NS-4C, the GW1NS-4 has no built-in Cortex-M3 processor, and the GW1NSER-4C offers one-time programming and authentication code features. -
Page 11: A Development Board Suite
A development board suite includes the following items: DK_START_GW1NSR-LV4CQN48PC7I6_V1.1 USB Cable Quick Start Guide Figure 2-2 A Development Board Suite Gowin DK_START_GW1NSR- LV4CQN48PC7I6_V1.1 Development Board USB Mini Data Line Quick Start User Manual ① DK_START_GW1NSR-LV4CQN48PC7I6_V1.1 Development Board ②... -
Page 12: Pcb Components
2 Development Board Introduction 2.3 PCB Components 2.3 PCB Components Figure 2-3 PCB Components 1.2V 2.5V 3.3V 1.8V LVDS/MIPI Input 5V IN Download USB/J-Link Select FPGA GPIO Reset J-Link LVDS/MIPI Output (MCU Debug) DBUG388-1.0E 5(22) -
Page 13: System Block Diagram
2 Development Board Introduction 2.4 System Block Diagram 2.4 System Block Diagram Figure 2-4 System Block Diagram 5 Pairs LVDS/MIPI INPUT 1*BUTTON 1*UART 1*LED GPIO FPGA 1*SPI Flash 50MHz 4Pairs LVDS/MIPI 4*SWITCH OUTPUT 1.2V/1.8V/2.5V/ 3.3V J-Link FT232HL MINI USB 2.5 Features The structure and feature of the development board are as follows: 5. -
Page 14: Development Board Specification
2 Development Board Introduction 2.6 Development Board Specification 8. Key switch and slide switch One reset button One key switch 9. LED One power indicator (green) 1 LEDs (green) One Key indicator (green) 10. Memory 1Mbit embedded Flash ... - Page 15 2 Development Board Introduction 2.6 Development Board Specification Functional Item Technical Condition Remarks Description Reset button Reset for FPGA – Test indicator, Key Four Test indicators, green indicator, Power One Power indicator, green – indicator One Key indicator, green Crystal Provide 50MHz Package5032...
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Page 16: Development Board Circuit
3 Development Board Circuit 3.1 FPGA Module Development Board Circuit 3.1 FPGA Module Overview For the resources of GW1NSR series of FPGA Products, please refer DS861, GW1NSR series of FPGA products. For the resources of GW1NSER series of FPGA Products, please refer DS881, GW1NSER series of SecureFPGA Products Data Sheet. -
Page 17: Usb
3 Development Board Circuit 3.2 Download & Debug 3.2.2 USB Figure 3-1 Connection Diagram for FPGA USB 3.2.3 J- LINK Figure 3-2 FPGA J-LINK Connection Diagram 20PIN_2.54mm间距 双列排针 GW1NS4/GW1NSR4/GW1NSER4 3.2.4 Procedure 1. FPGA and MCU Download Mode: Plug the USB cable to the development board USB interface (J6). Note! Before downloading, switch the SW3, SW4, SW5, and SW6 on the development board to FT232 side. -
Page 18: Pins Distribution
3 Development Board Circuit 3.3 Power Supply 3.2.5 Pins Distribution Table 3-1 FPGA Download Pins Distribution Signal Name Pin No. BANK Description I/O Level JTAG Signal 3.3 V /2.5 V /1.2V 3.3 V /2.5 V /1.2V JTAG Signal 3.3 V /2.5 V /1.2V JTAG Signal 3.3 V /2.5 V /1.2V JTAG Signal... -
Page 19: Power System Distribution
3 Development Board Circuit 3.4 Clock, Reset 3.3.2 Power System Distribution Figure 3-3 Power System Distribution Interface DC5V Input USB2JTAG （FT232） TPS7A7001 3.3V UART&KEY&LED& RST&CLK FPGA VCCO3 TPS7A7001 1.8V FPGA VCCO0&1 (Flash) FPGA VCCX VCCO2(LVDS) TPS7A7001 2.5V FPGA VCCO0&1 （LVDS） FPGA VCCO2 VCCO0&1 TPS7A7001... -
Page 20: Overview
3 Development Board Circuit 3.5 LED 3.4.1 Overview The development board provides a 50MHz crystal oscillator connected to the PLL input pin. This can be employed as the input clock for the PLL in FPGA. Frequency division and multiplication of PLL can output the clock required by the user. -
Page 21: Led Circuit
3 Development Board Circuit 3.6 Switches 3.5.2 LED Circuit Figure 3-5 LED Circuit VCC3P3 F_LED1 LED1 GW1NS4/GW1NSR4/GW1NSER4 3.5.3 Pins Distribution Table 3-4 LED Pins Distribution Signal Name Pin No. BANK Description I/O Level F_LED1 LED1 2.5V / 1.2V 3.6 Switches 3.6.1 Overview There are four slide switches in the development board to control program downloading and MCU debugging. -
Page 22: Key Circuit
3 Development Board Circuit 3.8 GPIO 3.7.2 Key Circuit Figure 3-6 Key Circuit Diagram VCC3P3 KEY1 KEY1 SN74A F_KEY1 VC4T2 GW1NS4/GW1NSR4/GW1NSER4 3.7.3 Pins Distribution Table 3-5 Key Circuit Pins Distribution Signal Name Pin No. BANK Description I/O Level F_KEY1 KEY1 1.8V 3.8 GPIO 3.8.1 Overview... -
Page 23: Gpio Circuit
3 Development Board Circuit 3.8 GPIO 3.8.2 GPIO Circuit Figure 3-7 GPIO Circuit 3.8.3 Pins Distribution Table 3-6 J17 GPIO Pins Distribution Signal Name Pin No. Socket Pin No. BANK Description I/O Level General I/O H_B_IO7 2.5V/1.8V/1.2V General I/O 2.5V/1.8V/1.2V H_B_IO8 General I/O 2.5V/1.8V/1.2V... -
Page 24: Mipi/Lvds
3 Development Board Circuit 3.9 MIPI/LVDS 3.9 MIPI/LVDS 3.9.1 Overview Two 10P double columns with 2 mm pitch are reserved on the development board for MIPI/LVDS input/output testing and high speed data communication. 3.9.2 MIPI/LVDS Circuit Figure 3-8 LVDS Circuit F_LVDS_A1_P F_LVDS_A1_N F_LVDS_B1_P... -
Page 25: Pins Distribution
3 Development Board Circuit 3.9 MIPI/LVDS 3.9.3 Pins Distribution Table 3-7 J15 FPGA Pin Distribution Signal Name Pin No. Socket Pin No. BANK Description I/O Level Differential output 2.5V(LVDS)/ F_LVDS_A1_P channel 1+ 1.2V(MIPI) Differential output 2.5V(LVDS)/ F_LVDS_A1_N channel 1- 1.2V(MIPI) Differential output 2.5V(LVDS)/ F_LVDS_A2_P... -
Page 26: Table 3-8 J16 Fpga Pin Distribution
3 Development Board Circuit 3.9 MIPI/LVDS Table 3-8 J16 FPGA Pin Distribution Signal Name Pin No. Socket Pin No. BANK Description I/O Level Differential input 2.5V / 1.2V F_LVDS_B1_P channel 1+ (LVDS/MIPI) Differential input 2.5V / 1.2V F_LVDS_B1_N channel 1- (LVDS/MIPI) Differential input 2.5V / 1.2V... -
Page 27: Rs232
3 Development Board Circuit 3.10 RS232 3.10 RS232 3.10.1 Overview One RS232 interface is reserved on the development board for the FPGA to communicate with PC or the other devices. 3.10.2 RS232 Circuit Figure 3-9 RS232 Download Connection 3.10.3 Pins Distribution Table 3-9 RS232 Pins Distribution Signal Name Pin No. -
Page 28: Precautions
MIPI I. 6. GW1NSER-4C is GOWIN SecureFPGA with Secure Mode and Authentication Code. 7. Gowin version1.9.5 and above is required to develop the GW1NSER-4C device. 8. Carefully use the “Secure Mode" of one-time programming for product delivery. During factory debugging, it is recommended not to use the "Secure Mode"... -
Page 29: Gowin Software
5 Gowin Software Gowin Software Please refer to SUG100, Gowin Software User Guide for details. DBUG388-1.0E 22(22)
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