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Related Manuals for GOWIN DK START GW1NSR-LV4CQN48PC7I6 V 1.1
Summary of Contents for GOWIN DK START GW1NSR-LV4CQN48PC7I6 V 1.1
- Page 1 DK_START_GW1NSR-LV4CQN48PC7I6_V User Guide DBUG388-1.1E, 07/30/2021...
- Page 2 Copyright © 2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved. , Gowin and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark Office, and other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders.
- Page 3 Revision History Date Version Description 01/21/2021 1.0E Initial version published. 07/30/2021 1.1E The Quick Start in 2.2 A Development Board Suite deleted.
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Page 4: Table Of Contents
Contents Contents Contents ....................... i List of Figures ....................iii List of Tables ...................... iv 1 About This Guide ..................1 1.1 Purpose ..........................1 1.2 Related Documents ......................1 1.3 Terminology and Abbreviations ................... 2 1.4 Support and Feedback ....................... 2 2 Development Board Introduction .............. - Page 5 3.9.1 Overview ........................15 3.9.2 MIPI/LVDS Circuit ......................16 3.9.3 Pinout ..........................16 3.10 RS232 ..........................18 3.10.1 Overview ........................18 3.10.2 RS232 Circuit ....................... 18 3.10.3 Pinout ........................... 19 4 Considerations .................... 20 5 Gowin Software ................... 21 DBUG388-1.1E...
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Page 6: List Of Figures
List of Figures List of Figures Figure 2-1 DK_START_GW1NSR-LV4CQN48PC7I6_V1.1 Development Board ......3 Figure 2-2 A Development Board Suite ..................... 4 Figure 2-3 PCB Components ......................5 Figure 2-4 System Block Diagram ..................... 5 Figure 3-1 FPGA and USB Connection Diagram ................10 Figure 3-2 FPGA and J-LINK Connection Diagram ................ - Page 7 List of Tables List of Tables Table 1-1 Terminology and Abbreviations ..................2 Table 2-1 Development Board Specification ..................7 Table 3-1 FPGA Download Pinout ..................... 11 Table 3-2 FPGA Power Supply Pinout ....................12 Table 3-3 FPGA Clock and Reset Pinout ................... 12 Table 3-4 LED Pinout .........................
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Page 8: About This Guide
1. DS821, GW1NS series FPGA Products Data Sheet 2. UG823, GW1NS series of FPGA Products Package and Pinout Manual 3. UG824, GW1NS-4&4C Pinout 4. UG290, Gowin FPGA Products Programming and Configuration Guide 5. SUG100, Gowin Software User Guide DBUG388-1.1E 1(21) -
Page 9: Terminology And Abbreviations
Serial Peripheral Interface Phase-locked Loop QN48 QFN48 1.4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly by the following ways. Website: www.gowinsemi.com E-mail: support@gowinsemi.com... -
Page 10: Development Board Introduction
2 Development Board Introduction 2.1 Overview Development Board Introduction Taking GW1NSR-4C for an instance, this chapter mainly introduces the composition, functions and features of the development board. Compared to the GW1NS-4C, the GW1NS-4 has no built-in Cortex-M3 processor, and the GW1NSER-4C offers one-time programming and authentication code features. -
Page 11: A Development Board Suite
2 Development Board Introduction 2.2 A Development Board Suite provide excellent calculation functions and exceptional system response interrupts. They also offer high performance, low power consumption, flexible usage, instant start-up, affordability, nonvolatile, high security, and abundant package types, among other benefits. The development board offers abundant external interfaces, including MIPI/LVDS interfaces, GPIO interfaces, etc. -
Page 12: Pcb Components
2 Development Board Introduction 2.3 PCB Components 2.3 PCB Components Figure 2-3 PCB Components 1.2V 2.5V 3.3V 1.8V LVDS/MIPI Input 5V IN Download USB/J-Link Select FPGA GPIO Reset LVDS/MIPI Output J-Link (MCU Debug) 2.4 System Block Diagram Figure 2-4 System Block Diagram 5 Pairs LVDS/MIPI INPUT 1*BUTTON 1*UART... -
Page 13: Features
2 Development Board Introduction 2.5 Features 2.5 Features The structure and feature of the development board are as follows: 1. FPGA Adopts QN48 package Up to 38 user I/O Embedded flash, data not easily lost if power down ... -
Page 14: Development Board Specification
2 Development Board Introduction 2.6 Development Board Specification 2.6 Development Board Specification Table 2-1 Development Board Specification Item Functional Description Technical Condition Note FPGA Core chip – – Support an USB USB to JTAG chip interface; Support Download – integrated on board JTAG, AUTOBOOT ... - Page 15 2 Development Board Introduction 2.6 Development Board Specification Item Functional Description Technical Condition Note RS232 Used for testing One RS232 – USB interface ESD protection: ±15kV non-contact discharge, ± 8kV contact discharge; USB interface: ESD protection; Schottky diode is Protection Power interface: connected between...
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Page 16: Development Board Circuit
3 Development Board Circuit 3.1 FPGA Module Development Board Circuit 3.1 FPGA Module Overview For the resources of GW1NS series of FPGA Products, please refer to DS861, GW1NSR series of FPGA Products Data Sheet. I/O BANK Introduction For the I/O BANK information and package and pinout information, please refer to UG863, GW1NSR series of FPGA Products Package and Pinout User Guide. -
Page 17: Usb
3 Development Board Circuit 3.2 Download & Debug 3.2.2 USB Figure 3-1 FPGA and USB Connection Diagram 3.2.3 J- LINK Figure 3-2 FPGA and J-LINK Connection Diagram 20PIN_2.54mm pitch Double Row Pin GW1NSR-LV4CQN48PC7I6_V1.1 3.2.4 Procedure 1. FPGA and MCU Download Mode: Plug the USB cable to the development board USB interface (J6). -
Page 18: Pinout
3 Development Board Circuit 3.3 Power Supply 3.2.5 Pinout Table 3-1 FPGA Download Pinout Signal Name Pin No. BANK Description I/O Level JTAG Signal 3.3V/2.5V/1.2V JTAG Signal 3.3V/2.5V/1.2V JTAG Signal 3.3 V/2.5V/1.2V JTAG Signal 3.3V/2.5V /1.2V MODE0 Mode selection pin 3.3V/2.5V/1.2V JTAGSEL_N JTAGSEL_N... -
Page 19: Power Supply Pinout
3 Development Board Circuit 3.4 Clock, Reset 3.3.3 Power Supply Pinout Table 3-2 FPGA Power Supply Pinout Signal Name Pin No. BANK Description I/O Level VCCO0 I/O Bank Voltage 2.5V/1.8V/1.2V VCCO1 I/O Bank Voltage 2.5V/1.8V/1.2V VCCO2 I/O Bank Voltage 2.5V/1.2V VCCO3 12, 24 I/O Bank Voltage... -
Page 20: Led
3 Development Board Circuit 3.5 LED 3.5 LED 3.5.1 Overview There is one green LED in the development board and users can display the required status through the LED. There are two LEDs left to facilitate the observation of power supply and FPGA loading status. You can test the LEDs in the following ways: When the FPGA corresponding pin output signal is logic low, the LED is ... -
Page 21: Key
3 Development Board Circuit 3.7 Key 3.7 Key 3.7.1 Overview There is one key switch in the development board. Users can manually input low level to the corresponding FPGA pins for testing purposes. 3.7.2 Key Circuit Figure 3-6 Key Circuit Diagram 3.7.3 Pinout Table 3-5 Key Circuit Pinout Signal Name... -
Page 22: Gpio Circuit
3 Development Board Circuit 3.9 MIPI/LVDS 3.8.2 GPIO Circuit Figure 3-7 GPIO Circuit 3.8.3 Pinout Table 3-6 J17 GPIO Pinout Signal Name Pin No. Socket Pin No. BANK Description I/O Level H_B_IO7 General I/O 2.5V/1.8V/1.2V H_B_IO8 General I/O 2.5V/1.8V/1.2V H_B_IO9 General I/O 2.5V/1.8V/1.2V 3.9 MIPI/LVDS... -
Page 23: Mipi/Lvds Circuit
3 Development Board Circuit 3.9 MIPI/LVDS 3.9.2 MIPI/LVDS Circuit Figure 3-8 LVDS Circuit F_LVDS_A1_P F_LVDS_A1_N F_LVDS_B1_P F_LVDS_B1_N F_LVDS_A2_P F_LVDS_A2_N F_LVDS_B2_P F_LVDS_B2_N F_LVDS_A3_P F_LVDS_A3_N F_LVDS_B3_P F_LVDS_B3_N F_LVDS_A4_P F_LVDS_A4_N F_LVDS_B4_P F_LVDS_B4_N F_LVDS_B5_P F_LVDS_B5_N 3.9.3 Pinout Table 3-7 J15 FPGA Pinout FPGA Socket Signal Name BANK Description... -
Page 24: Table 3-8 J16 Fpga Pinout
3 Development Board Circuit 3.9 MIPI/LVDS FPGA Socket Signal Name BANK Description I/O Level Pin No. Pin No. Differential output 2.5V(LVDS)/ F_LVDS_A4_P channel 4+ 1.2V(MIPI) Differential output 2.5V(LVDS)/ F_LVDS_A4_N channel 4- 1.2V(MIPI) Table 3-8 J16 FPGA Pinout FPGA Socket Signal Name BANK Description I/O Level... -
Page 25: Rs232
3 Development Board Circuit 3.10 RS232 FPGA Socket Signal Name BANK Description I/O Level Pin No. Pin No. 2.5V/1.2V Differential input F_LVDS_B4_P channel 4+ (LVDS/MIPI) 2.5V/1.2V Differential input F_LVDS_B4_N channel 4- (LVDS/MIPI) 2.5V/1.2V Differential input F_LVDS_B5_P channel 5+ (LVDS/MIPI) 2.5V/1.2V Differential input F_LVDS_B5_N channel 5-... -
Page 26: Pinout
3 Development Board Circuit 3.10 RS232 3.10.3 Pinout Table 3-9 RS232 Pinout Signal Name Pin No. BANK Description I/O Level Serial data UART_TXD 1.8V Sends from FPGA Serial data UART_RXD 1.8V Sends to FPGA DBUG388-1.1E 19(21) -
Page 27: Considerations
4 Considerations Considerations Considerations for use of the development board: 1. Handle with care and pay attention to electrostatic protection; 2. Before downloading from FPGA and MCU, switch SW3、SW4、SW5、 SW6 to the FT232 side; 3. Before MCU Debugging, switch the SW3, SW4, SW5, and SW6 on the development board to J-Link side;... -
Page 28: Gowin Software
5 Gowin Software Gowin Software Please refer to SUG100, Gowin Software User Guide for details. DBUG388-1.1E 21(21)
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